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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tony Viola who wrote (61644)	6/13/1999 2:57:00 PM
From: kash johal	Respond to of 1573941

Tony, Re:" Everything is a tradeoff, still. If you go too far with the cycle time thing, i.e., building for Megahertz to the extreme, you can end up using a lot more logic, hence transistors, hence real estate. I'm sure Dirk got it balanced just right though, right?" You are right that you can keep pipelining and increasing the Mhz without any effective performance increase. The great news is that even with the increased pipeling the K7 is still faster than the Xeon core in Integer and MUCH faster in FP. All this on a clock by clock analysis. I have listened to the real audio link and Dirk(and the AMD design team) is indeed impressive. 1. They wrote their own hi-level sub-set version of Verilog to enable fast system level simulation. This was very clever - as general purpose Verilog is very powerful - but the synthesis can provide poor results in performance/area leading to endless synthesis runs. 2. The other advantage to their sub-set was it voided the need for synthesis. This design style is very gate count inefficent but cut design times. 3. They hand placed their std. cells by hand. Placement is very critical these days. This probably resulted in slow placement but high performance. 4. They used ther auto-router to connect all the signals. This led to a fast design cycle - from concept to first silicon in 18 months or so. This also means that they probably can gain quite a bit from the speed work of analyzing the longest wires. 5. They appeared to have an excellent management of the design process: from topdown system level design to a very flat structure for managing the individual tasks - with senior designers leading each task. The only downside is they may have been able to squeeze more gates out of the design and by going custom blocks vs std cell they may have saved 10% in chip area. As Scumbria has stated here already: An absolutely superb job of managing and executing a major design in record time with high probability of first time success. The issues are pretty clear I think: Brilliant design, optimized for high-yeild and performance leaves the competition stunned. Wether the Fab 30 manufacturing guys can deliver equally stunning performance will determine the future. If the 0.18/Cu doesn't yield by year end all of this great effort will have gone for nought. The glass is half-full right now and everybody knows it. Regards, Kash

To: Tony Viola who wrote (61644)	6/13/1999 3:03:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1573941

Tony, Everything is a tradeoff, still. If you go too far with the cycle time thing, i.e., building for Megahertz to the extreme, you can end up using a lot more logic, hence transistors, hence real estate. I'm sure Dirk got it balanced just right though, right? Actually, in some ways the opposite is true. It requires a lot less logic to build a deep pipeline than short one. The reason being that deep pipelines are inherently simpler, and have fewer timing problems (if architected properly.) Scumbria