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To: Tom Shutters who wrote (3715)	6/14/1999 4:46:00 PM
From: Tom Shutters	Respond to of 4005

Another from Electronic Buyers' News "VLSI retools prototyping system to reduce SOC design costs" "Silicon Valley- Tackling the challenge of producing increasingly complex ASICs for ever-decreasing design cycles, VLSI Technology Inc. today will unveil its second-generation Rapid Silicon Prototyping system, which is designed to cut system-on-a-chip development time in half." "A series of enhancements to the original RSP platform-including a host of new reusable intellectual-property blocks-have resulted in the RSP7+, which supports million-gate SOC ASICs going into network peripherals, virtual private networks, and other ARM CPU-based systems that require wired connectivity." "The lack of commercially available proven and reusable IP has become a bottleneck in the design of multimillion-gate chips."... ..."The RSP7+ platform also features a 470,000-gate ProASIC FPGA from Actel Corp. that customers can use to test-drive new IP or program last-minute design tweaks, according to Jacot." techweb.com