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Technology Stocks : Apple Inc. -- Ignore unavailable to you. Want to Upgrade?

To: J R KARY who wrote (25146)	6/15/1999 11:39:00 PM
From: Dirk Dawson	Respond to of 213182

That would be the vaunted "Silicon On Investor" prize, right <g>?

To: J R KARY who wrote (25146)	6/16/1999 12:14:00 AM
From: Richard Habib	Read Replies (1) \| Respond to of 213182

Hey Jim, I'm posting that article as it's a good read. Also I save these links and the SI archives seem to stay active long after other links have been broken. Rich IBM Preps SOI-Based PowerPCs (06/15/99, 7:44 p.m. ET) By Anthony Cataldo, EE Times IBM Microelectronics is in the final stage of debugging PowerPC microprocessors that feature copper interconnects and silicon-on-insulator (SOI) technology, which is expected to boost the processors' performance by about 30 percent over current copper-based devices at equivalent frequencies. IBM's first 0.22-micron devices with these features will be used in Apple Computer's Macintosh systems and in IBM servers, perhaps within two to three months. At the same time, IBM is developing a 1-GHz PowerPC that will be built on a 0.18-micron process and will try to steal some of the limelight from Intel's second-generation IA-64 chip, dubbed McKinley. At the VLSI Technology Symposium n Kyoto, Japan, IBM presented a paper describing a 64-bit PowerPC with 34 million transistors, a 670-MHz clock, six layers of copper interconnect and SOI. The chip will include 256 kilobytes of instruction/data level-one cache, and 104 x 16-kilobit L2 director cache. The 139- mm2 device has an internal 1.8-V core operating voltage, uses a 3.3-V supply voltage and dissipates 24 watts. The PowerPC chip will be among the first SOI-based products from IBM, which announced last year that it had successfully developed the technology after about 20 years of research. While copper metallization works to reduce the resistance among the multiple wiring layers of a chip, SOI increases the basic transistor switching speed by burying a sheath of oxideinsulator material below the source and drain of a transistor to isolate it from the silicon substrate. According to IBM, this increases the chip's current by 10 to 15 percent, and eliminates performance-limiting area junction capacitance and the reverse MOS body effect of conventional "bulk" silicon wafers. Though IBM has not made an official product announcement of the SOI-based PowerPC, the device will be production ready for server products once debugging is complete in the next two to three months, said Ghavam Shahidi, senior SOI program manger at IBM Microelectronics, in Yorktown Heights, N.Y. Possibly before that chip is announced, IBM will start to deliver a slower PowerPC 750 to Apple that uses SOI and the same process technology, Shahidi said. Each of the SOI-based processors exhibit performance improvements over previous-generation processors of "greater than 30 percent," Shahidi said. Meanwhile, IBM is in now developing its 0.18-micron and 0.13-micron SOI generations for PowerPC chips. Shahidi said IBM plans to detail a 64-bit PowerPC with a 1-GHz clock at the Hot Chips conference at Stanford University later this summer, and may announce its 0.18-micron SOI process technology at the International Electron Device Meeting later this year. The 1-GHz device will be used in IBM's RS/6000 server series. The chip is slated for introduction in 2001, and will go toe-to-toe with Intel's McKinley processor, Shahidi said. McKinley, Intel's second-generation IA-64 processor, is expected to appear late in 2001. Initially, Intel will use a 0.18-micron process technology to make the part, but is expected to migrate to a 0.13-micron process with copper interconnects the following year. Compared to current copper-based PowerPC chips from IBM that use bulk technology, IBM was able to cut channel switching delay using SOI and thereby significantly boost chip performance. Shahidi said a ring oscillator circuit, a widely-used industry benchmark to measure transistor speed, has a delay of less than 10 picoseconds with a channel length of 0.12 microns using an 0.22-micron CMOS process. That's comparable to transistor speeds exhibited by Intel's 0.18-micron process based on bulk CMOS, which uses shorter channel lengths because of its smaller line widths, Shahidi said. IBM's SOI technology employs a partially depleted insulator that is about 1,000 angstroms thick, which is about double the thickness of fully depleted material used by other companies such as Motorola, Shahidi said. Using partially depleted devices has several advantages over a fully depleted approach, including the ability to use multiple threshold voltages, better manufacturing characteristics and good scalability, he said.