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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (31060)	6/16/1999 8:50:00 PM
From: Proud_Infidel	Read Replies (1) \| Respond to of 70976

Sematech tries to link pace of technology to bottom line By J. Robert Lineback AUSTIN, Tex.. - Sematech is working on a new planning tool that analysts say is badly needed by the semiconductor industry. The semiconductor consortium is trying to fill what it calls a major void in the industry's ability to determine whether it makes economic sense to accelerate new chip technologies or move to larger 300-mm wafers. After nearly a year of meetings, workshops, and trend analyses, Sematech is now refining an economic model that could be used to assess the impact of industry technology roadmaps and new generations of fab gear on semiconductor profitability. The consortium plans to unveil its economic model to industry executives in June at a board meeting of its international subsidiary in South Korea. The model is not intended to give semiconductor makers push-button answers to what-if questions. "It is not a magic formula that tells us how to proceed with development," cautions Frank Robertson, chief operating officer of the chip consortium. "It is a vehicle for a dialogue." The model will set up a wide range of factors that affect industry economics and the profitability of next-generation technologies. The aim is to help companies establish the tradeoffs of two- and three-year technology cycles with manufacturing options -- whether or not to upgrade a fab, build a new plant, or use an outside foundry. Also being plugged into the model will be the economic health and growth of major chip applications such as PCs and mobile communications, as well as macroeconomics and regional conditions. While Sematech's new model won't spit out business plans and strategies, it is expected to draw a lot more industry attention to issues that go beyond pure technology, predict analysts who are delighted with the consortium's efforts to come up with an economic model for the industry. Even the Semiconductor Industry Association (SIA) may be interested in adding parts of the Sematech economic model to its 2001 update of the international technology roadmap, comments Juri Matisoo, vice president of the trade group's technology programs in San Jose. That kind of addition would go a long way in making the document a more complete planning tool, according to industry analysts. An earlier version of the Sematech model was previewed to some 40 executives from capital equipment suppliers and chip makers at a May workshop in San Francisco. Once it's ready, the model will be shared by Sematech with the rest of the industry. "This is a high-level model of the industry's dynamics," explains Sematech's Robertson, that can be used to look at "what are the implications for [equipment] supplier development and payback, as well as what are the implications for chip maker investment and payback." "We are not talking about a plan or an economic roadmap," he says. "We are talking about a common understanding of the implications and economics relative to technology acceleration and 300-mm." It's up to the individual companies to use it, he adds. Sematech began its efforts to understand industry economics last year after the 300-mm movement stalled. Capital-equipment suppliers and chip makers blamed each other for wasting billions of dollars on R&D when the move to bigger wafers was delayed by the business downturn and the cost advantages of device shrinks. There have been previous attempts to figure out the tradeoffs in moving to new technology. "An early-level model compared the economics of a 200-mm fab at a given technology node and a 300-mm fab at a different process node, but [now] the issues have been expanded to cover the more important issues of what's driving the next fab," says Paul Peercy, president of the SEMI/Sematech team representing equipment and materials suppliers in Austin. The issues contained in the Sematech model include the frequency of technology nodes (two vs. three years); the growth and health of semiconductor applications (such as PCs), the tradeoffs of upgrading fabs versus building new ones; and the emergence of foundries as a viable option for integrated device manufacturers. "The hope is that the industry can plan its future a little better," Peercy adds. "There is a precedent for this kind of activity. Sematech and SEMI/Sematech held a series of capital productivity workshop meetings in 1994 and 1995 to look at the [economic] requirements for moving to quarter-micron and 200-mm wafers. It was considered quite successful," he adds. Analysts tracking chip technologies are giving Sematech high marks for moving to fill what many of them believe has become a major gap in the industry's ability to assess the ramifications of technology acceleration. The inability to comprehend fully the impact of rapid process shrinks in recent years has been blamed by analysts and industry managers alike as a contributing factor in glutting chip markets during the past downturn. Now, technologists are debating a proposal to accelerate technology nodes in the 1999 update of the SIA's International Technology Roadmap for Semiconductors (see "Debate still rages over aggressive roadmap" in the current publication). "The major problem with the technology roadmap is that it does not address the economic issues," maintains Ronald Dornseif, the analyst tracking wafer-processing technology at Dataquest in San Jose. "This is an excellent move by Sematech," he adds, "because this [model] will increase the dialogue beyond just the technology." Too much attention has been placed on computers as the prime application driving U.S. industry roadmaps, notes the Dataquest analyst. He says that more emphasis must be placed on communications applications and wireless systems. Product and market trends will also impact a range of capital spending issues. "If system-level integration [SLI] becomes a dominate issue," says Dornsief, "the economics of SLI will dictate that fabs must deal with short-run products as opposed to DRAMs or microprocessors. You will have the economic issue of mask-making if product runs are shorter," he says, referring to the trend to use more expensive phase-shifting reticles instead of moving quickly to new-generation lithography tools with narrow-wavelength exposures. "This could determine when post-optical lithography is needed in the next decade," adds the analyst. The lack of economic data and business models when charting the chip technology has clouded the potential benefits of technology roadmaps, believes analyst G. Dan Hutcheson, president of VLSI Research Inc. in San Jose. "Many people have begun to blame the roadmap for their problems, but companies were the ones that decided to take all of the potential savings and pour them into another CD [critical-dimension shrink]," he exclaims. Hutcheson figures the accelerated technology roadmaps put out by the SIA have saved the industry money by shrinking the time that it takes to develop a process generation from three to two years. He estimates the industry is getting a 640% return on every dollar spent on producing the SIA roadmaps. "When you figure in the salaries and benefits of people attending the meetings, travel and other expenses, each SIA roadmap costs about $50 million to complete."