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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (62018)	6/16/1999 6:46:00 PM
From: kash johal	Respond to of 1571927

Petz, Re:"The article does say that 2.5v is reduced to 1.6v for "oxide reliability issues." But how is a chip made with varying oxide thickness over its real estate. Is it even possible to have a chip with the PLL (~one square mm) having a thinner oxide layer than the rest of the chip (183 square mm)?" I had agreed with Paul originally but I now suspect that they are running at 1.6V as well. They have probably lowered the vt's down from 0.6 to 0.3 range and it is still a 0.25 micron process. Yes dual gate oxides are pretty normal. You need the ticker gate oxides for the I/O region. And yes this whole article is very confusing. PS Paul had posted power of >60 watts and I believe he is right. I have read Icc of 40 AMps and with Vcc of 1.6 that gives us 64 watts. We will have to wait for the specs but the whole situation is very interesting. Regards, Kash

To: Petz who wrote (62018)	6/16/1999 7:19:00 PM
From: Shane Geary	Read Replies (2) \| Respond to of 1571927

Petz - Re: " But how is a chip made with varying oxide thickness over its real estate." As Kash said, in some circles it's pretty standard to have dual gate oxides on a single wafer. Eg if you want 3.3V and 5V transistors on the one chip. One way to do it... Say you want 35A and 75A Tox. Grow most of your thick gate ox (about 65A at a guess) over all device regions. Mask the areas where you want to keep the thick oxide and strip away the rest. Then grow 35A of oxide. The 65A will grow to 75A. Hey presto - dual gate oxide.

To: Petz who wrote (62018)	6/16/1999 9:16:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 1571927

Petz - Re: "Is it even possible to have a chip with the PLL (~one square mm) having a thinner oxide layer than the rest of the chip (183 square mm)?" Sure - it is possible, but very difficult and expensive. One oxide area needs to be masked - with a high temp. film such as SiN - while oxide in the remaining thin-ox areas is grown to a different thickness. This is not a good idea, generally, due to contamination of the original oxide when the masking film is stripped. I would doubt that AMD is doing this. They may have low threshold transistors - implemented with ion implants - in the PLL and want to keep the operating voltage low due to the high frequencies - but that's just a wild guess. Paul