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To: Tony Viola who wrote (83693)6/17/1999 12:15:00 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
Tony - Re: "I don't know if Intel has ECC on caches, TLBs, microcode. "

Intel's XEONS - and I think the "newer" Pentium II's and all IIIs have ECC on the L2 caches - detect/correct 1 bit, detect 2 bit.

Whatever microcode instructions they have are implemented in hard logic and/or "reprprogramable" flash. These are not subject to soft error upset.

Re: "if the alpha or other particle hits a critical logic latch, it's probably sayonara, since it's so hard to predict what combinations of latches to cover with ECC, so computer designs don't try, to my knowledge. "

That sounds about right - but the actual ability of an alpha particle to cause such an upset is only recently a concern for random logic - as opposed to DRAM (and SRAM) where these concerns have been a reality for 23 years.

Paul



To: Tony Viola who wrote (83693)6/18/1999 12:38:00 AM
From: Amy J  Respond to of 186894
 
Thanks Tony,

Interesting post.

I wonder if there's any statistical estimate on potential frequency?

Regards,

Amy J