Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (62097)	6/17/1999 11:04:00 AM
From: Yousef	Read Replies (1) \| Respond to of 1571707

Ali, Re: "How come everyone are making I/O part of chips running at 3.3V while the core runs at about 2V WITHOUT MAKING DIFFERENT OXIDE THICKNESS FOR DIFFERENT CHIP PARTS?" My "dear", ignorant Ali ... You need to "study up" on your circuit design techniques. By stacking FET's, you can produce a larger voltage swing WITHOUT requiring that the gate oxide "see" those larger voltages. Only the Source/Drain diodes must be able to handle these voltages. Please try to "think" before posting next time, TIA. Make It So, Yousef