Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Shane Geary who wrote (62158)	6/17/1999 3:53:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1575063

Re: "TSMC (the kings of manufacturability and stable processes) recently said that they purposely sited their Leff larger than Intel's to minimise leakage." And why would punch through be such a problem? EP

To: Shane Geary who wrote (62158)	6/19/1999 12:17:00 PM
From: Yousef	Respond to of 1575063

Shane, Re: " You're being a bit too black-and-white here Yousef. Smaller Leff in itself is not enough to say whether one process is better than another." Shane ... For a u-processor process, high drive currents at low operating voltage along with an interconnect that provides low R & C is what is necessary to achieve the highest speed performance. Off state - subthreshold leakage has not been that much of a problem for CPU designers (<3na/um) ... For other ASIC designs, the leakage currents are a very "big deal". This is why TSMC and others "worry" about this parameter. Make It So, Yousef