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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Process Boy who wrote (62234)	6/17/1999 10:28:00 PM
From: grok	Read Replies (1) \| Respond to of 1575427

RE: <Another approach is to (obviously?) optimize the isolation structures.> How does Intel achieve such high IDsat with low Ioff in 0.18u?

To: Process Boy who wrote (62234)	6/17/1999 11:39:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1575427

Re: "Shane and Elmer - Re: Ion vs. Ioff (sub-threshold leakage) Shane indicated TSMC goes with a relatively larger Leff to minimize gate leakage. Another approach is to (obviously?) optimize the isolation structures. " But what's the big deal with sub-threshold leakage? EP

To: Process Boy who wrote (62234)	6/18/1999 2:00:00 PM
From: Shane Geary	Respond to of 1575427

PB: Re: " TSMC goes with a relatively larger Leff to minimize gate leakage. Another approach is to (obviously?) optimize the isolation structures" Are we talking about the same thing here? To me, gate leakage is a leakage current through the gate oxide, rather than sub-threshold current between source and drain. Anyway, we are is severe danger of going off-topic here (well, too late I suppose) and boring people to death, even if anyone is reading. Yousef has a lot to answer for, for starting this off. Regards, Shane