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To: andy kelly who wrote (83795)	6/18/1999 12:42:00 PM
From: Paul Engel	Read Replies (5) \| Respond to of 186894

Andy - Re: "Is the problem in the 0.18 process or in the CuMine design?" Inherently, the problem is in the Coppermine design, but the Fab guys (actually, Technology Development) are bearing a lot of the brunt - and are now chartered to make some improvements in the front-end (transistor gates) of the process. Meanwhile, the design group is going over their simulations and attempting to find discrepancies - as to why the simulations don't match the actual results - and make appropriate design changes. As per Intel custom, a Task Force encompassing both groups has been convened in Oregon and has been fairly active for almost a month. Re: "When they say a two month delay, does that imply that the problem has already been identified and they know how to fix it? If not, how could they know so precisely how long the delay will be?" Incremental improvements to several process modules have been identified with "Mhz" gains estimated for each module. If these are all implemented as planned and achieve their targets, the Coppermine speed will be improved to meet the initial goals - just with process tweaks. November would give Intel enough time to implement the process changes, fine tune them, and get "first" samples out to customers. 100% Burn-in can be employed to cover reliability issues while the modified process is requalified. Re: "How could they start ramping FOUR fabs without knowing for sure that everything was working? I thought Intel would have tested to the extreme before committing to that extent." Intel has used SRAM test vehicles to debug the process and these have run at 900+ MHz with no problems. The actual Coppermine results have been a show-stopper for Intel and they haven't figured out yet why the part is not meeting performance specifications and targets. Re: "Could this be an indication that some new feature was added to the design at the "last minute"?" No - Intel RARELY adds features at the last minute. Designs are frozen WELL BEFORE the parts are committed to layout . Paul

To: andy kelly who wrote (83795)	6/18/1999 12:57:00 PM
From: Saturn V	Read Replies (1) \| Respond to of 186894

Ref- <Could you tell us what you conclude by reading between the lines of the Coppermine delay articles? > This is my best effort at reading between the lines on the Coppermine problems. The chip layout design was completed late -(March April 99) time frame.This would put first Silicon in early May. It takes several weeks just to verify the design, and after the Silicon is completely clean, a large number of samples have to be accumulated and burnt in for any reliability problems. To meet the announced schedule, the first Silicon design had to be close to perfectly clean, with no unexpected reliability problems ,caused by the new design or process. Coppermine has an extra metal layer over the other the Dixon shrink , the 0.18 micron design which is being manufactured satisfactorily. So it is possible that a new problem was discovered on the extra metal layer. It appears that the problem was discovered late, but is fixable by simple design change in the masks. [If process changes are required, the schedule impact would have been a lot worse.] If the design change is confined to the metal layer, the impact on the schedule is minimal. The Celeron design was introduced flawlessly. The first Silicon was perfect and the part went immediately to manufacturing. Unfortunately this is not the norm. At least a few design tweaks are required for most designs before they are production worthy. Unfortunately the Celeron history of a flawless first design was not repeated. All this is my best interpretation of what has been disclosed. I have fretted for the last six weeks over the status of Coppermine, and my worry was justified.