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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (62580)	6/20/1999 11:45:00 PM
From: Charles R	Respond to of 1572159

Tenchusatsu, <That's one advantage of a shared multiprocessor bus. So for two-to-four-way systems, Xeon will exhibit lower latencies than K7> I would like to see some data on this before such a judgement can be passed. K7 has an additional flag, compared to P6, for its cahe coherency protocol to identify "shared owned" data (my recollection from old Microprocessor Report K7 article). This should go a long way in increasing K7 performance in multi-processor shared memory server apps. If it is a message passing architecture a la Chorus then cache coherency does not matter. Chuck

To: Tenchusatsu who wrote (62580)	6/20/1999 11:49:00 PM
From: Ali Chen	Read Replies (2) \| Respond to of 1572159

Ten, < AMD's point-to-point bus and multiprocessor performance,> Man, do you have something better to spend your time instead generating irrelevant FUD? Last resort on your sinking ship? (Just joking...) <all the other processors must be notified separately> What makes you think that the "north" bridge can't send these messages simultaneously? Remember, every processor has a separate "bus", is not it? <After doing a little research into the subject, I learned a little something interesting about the K7's point-to-point bus> First, you seem to learn really "a little". Second, how did you manage to do a research on a non-disclosed-yet system architecture? Please stop your groundless FUD.