SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Scumbria who wrote (84179)6/22/1999 9:57:00 AM
From: greenspirit  Read Replies (1) | Respond to of 186894
 
Scumbria and thread, Article...Tough road ahead...

June 22, 1999

ELECTRONIC ENGINEERING TIMES : The road to the Internet is paved with Silicon." Intel CEO Craig Barrett served up that bromide a few weeks ago as the chip giant heralded its move to 300-mm wafers and copper-interconnect technology.

The silicon transition from 200 mm will increase the potential wafer yield twofold, with process savings on the order of 30 to 50 percent. Factor in the anticipated reduction in feature size as device geometries head toward 0.13 micron, and you're talking about a serious payoff in bigger, faster, denser chips.

But if the road to the Internet is paved with silicon, what paves the road to silicon? To systems?

The answer that will emerge in New Orleans this week at the Design Automation Conference is blood, sweat and tears. The leap to bigger wafers, finer design geometries and Internet-speed device specifications will only compound the challenges facing electronics design engineers. Achieving performance milestones will take not only a quantum leap in design productivity but also real breakthroughs in design reuse and system-on-chip design. The tasks are Herculean, the risks daunting.

Addressing them will require steep investments of valuable intellectual capital. Indeed, design engineers and design software companies are shouldering a disproportionate share of the technology risk while laboring in relative obscurity. Many of the companies have suffered depressed valuations even as the chip giants' and Internet companies' stock values have rocketed into the stratosphere.

EDAC and a handful of executives in the EDA community deserve credit for their efforts to elevate design automation to its rightful place alongside semiconductors, computers and the Internet as a world-shaping high-tech business. But once again, the DAC conference organizers, with their slavish program focus on "tools and design methods," have neglected the business side of the equation. The bias against mixing business with technology does not serve an industry hungry for guidance in tackling the manifold challenges of design engineering as the Internet steamroller reshapes the road to silicon.