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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Duker who wrote (31135)	6/23/1999 8:58:00 PM
From: Proud_Infidel	Read Replies (1) \| Respond to of 70976

Bell Labs builds 5-atom thick gate oxides By Margaret Quan EE Times (06/23/99, 8:05 p.m. EDT) MURRAY HILL, NJ -- Researchers at Bell Labs believe they have bought some time for silicon-based transistor technology by developing ultra-thin gate oxides that are only 5 atoms thick. The insulating layer of silicon dioxide in today's chips is on average 25 atoms thick. David Muller, a materials physicist at Bell, and Greg Timp, a solid state physicist at Bell, told EE Times they believe their work may be help extend the life expectancy for silicon-based transistor technology to 2012. The researchers also proved that a four-atom layer is the fundamental physical limit for silicon dioxide-based insulators. In recent years, the semiconductor industry has believed that the silicon dioxide layer, the critical insulating layer in silicon-based transistors, would be the limiting factor for producing increasingly smaller chips and researchers warned silicon-based transistor technology would run out of steam before 2005. By continually reducing both the gate oxide thickness and the length of the gate electrode, the semiconductor industry has doubled the transistor's switching speed every 18 to 24 months, following what is known as Moore's Law. But this reduction of thickness and length of the gate electrode has its limits. "As the semiconductor industry moves to small devices, it's been known that one of the first things they'll run into trouble with is the gate oxide because it's the smallest thing we have to control," said Bell researcher Timp."Shrinking the gate oxide is important because it allows one to get more current out of the switch with less voltage." Researchers David A. Muller, Greg Timp, and their Bell research colleagues Tom Sorsch, S. Moccio, F.H. Baumann, and K. Evans-Lutterodt created a 5-atom thick silicon dioxide layer which included the thinnest transition layer (where the silicon dioxide layer meets the silicon substrate) measuring about 1-atom-thick. The team used a rapid thermal oxidation technique to grow the silicon dioxide layer and still preserve the bulk properties of silicon dioxide. The process included a special in-situ cleaning of the wafer by exposing it to chlorine and ultraviolet light, a non-standard cleaning procedure designed by Bell researchers Yi Ma and Marty Green. The very flat wafer was then transferred under vacuum to a reactor where the oxide was grown at 1000 degrees Celsius in pure oxygen for 10 seconds. To measure the electronic structure and determine the electrical properties of the thin oxide layer, Muller used atomic-scale electron energy loss spectroscopy (EEL)by passing an electron beam of 100,000 volts through a sample. This allowed him to measure the atoms in the layer. "Every element has a unique energy loss and energy loss identified the atom and how it is bonded to a neighboring atom,"Muller explained. Muller and Timp say the results their team has gotten are reproducible and the techniques they've used are not far away from being used by chip manufacturers. Before companies begin building transistors with ultra-thin gate oxides, Timp noted that there is work to be done. Among them are: how do you stop the etch when there is only 6 angstroms of gate oxide, and is the gate oxide reliable and can it be produced in high enough yields? How do the Bell Labs researcher know 4-atom-thick gate oxides is the limit? From the EEs point of view, Muller said, quantum mechanics dictates silicon wave function spills into oxide layer and that leads to tunneling or leakage current. "When you bring two pieces of silicon together, the wave functions of both pieces spill over and tunnel through the oxide so the oxide is no longer an effective barrier," Muller explained In the chemists' view, in order for the oxygen to know it is in bulk silicon dioxide and thus preserve bulk silicon dioxide properties, it needs to know there are other oxygen atoms nearby. If the layer is too thin, then this isn't possible. "To make sub-100 nanometer length technology viable," Timp said,"one of the requirements is to ability to make a very thin gate oxide and nearly perfect interfaces. "By being able to do this, researchers can focus on other issues, such as alternative gate dielectrics and lithography technology." Asked how the team's work may impact the concerns of researchers like IBM's Bijan Davari, a senior semiconductor researcher who recently was reported in EE Times to say that CMOS process technology will hit by wall by 2004, Timp noted that Davari's concerns about lithography, reliability issues and gate leakage current issues are all valid. "It's a serious problem. We believe we've solved one piece of the problem, but it doesn't solve them all," Timp added. The researchers are publishing their findings in the June 24,1999 issue of the journal Nature. eetimes.com