summer's over and it's back to school, you technoweenies. thankfully, wirbel's been hitting the books for us: vitesse and "shock-tee" (Xaqti) briefly cited here ...
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Electronic Engineering Times
August 16, 1999, Issue: 1074
Section: News
Port's massive chip creates buzz, questions -- Network processor totes 17 RISC cores
Loring Wirbel
NORTH ANDOVER, MASS. - C-Port Corp. is lifting the lid on what is perhaps the most highly integrated single-chip contender in the burgeoning network processor market. The long-awaited C-5 digital communications processor, entering general sampling in September, integrates 17 RISC processors with several integer processors and look-up tables, crossing boundaries among header-parsing, line-aggregation and search-engine applications in an 838-pin package.
Such a massive shared-memory chip raises the question of whether its integration is too ambitious for a startup-a problem that plagued the ill-fated media processor of MicroUnity Systems Engineering Inc. That's why C-Port is leading off with the introduction of a development system and communication application libraries based on standard C calls, said chief technology officer David Husak. OEMs must become familiar with the development software, Husak said, before working with so highly integrated an architecture.
The multiple layers of programming give the C-5 a versatility that "may be necessary to appeal to a broad range of network equipment vendors," said Tom Nolle, president of market-analysis firm CIMI Corp. (Voorhees, N.J.)."C-Port has the most sizzle in the industry now, more than the other newcomers, since its chip performs a superset of header parsing and line aggregation functions," Nolle said.
The processor is binning out at approximately 200 MHz and will carry a high-volume price tag of $400.
Designs in which the C-5 already is being used include a reconfigurable switch/router interfacing to an optical dense wavelength-division multiplexing backbone, in which 18 functions can be implemented in six line cards; a Web load-balancing switch performing wire-speed parsing and classifying of packets; and an integrated access device aggregating many T1 controllers.
Nbase/Xyplex Corp. already is committed to using the C-5 in future architectures, and newcomers such as Sirocco Systems Inc. and Gotham Networks Inc. are evaluating system-level implementations of the C-5. Vijay Aggarwal, chief technology officer of Gotham, said that no other processor architecture demonstrates similar flexibility at I/O ports to define the ports at will as Ethernet, OC-3, OC-12 or other interfaces.
Nolle of CIMI predicted that C-Port's greatest competition will come not from other startups but from merchant players with large fabs and design resources, such as Intel and Texas Instruments, and from communication systems players with semiconductor expertise, such as Lucent Technologies and Nortel Networks. If any of the big players "pulls together something even halfway rational, their clout alone will be enough to contaminate at least part of C-Port's market," Nolle said.
But programs that emphasize DSP for general communications-processing duties, such as TI's Digital Thunder, may prove a tougher sell, Nolle added. "It's not clear the DSP-intensive functions like voice compression will be as important as anticipated, particularly if you can throw more bandwidth at the problem instead," Nolle said. "For the dumber access devices needing some signal processing, it probably will always be cheaper to use general-purpose DSPs than special communication processors with DSP blocks."
Inside the processor
The most striking feature of the C-5 is its layers of hierarchy. Like many multichannel controller designs, the C-5 features 16 independent channel processor blocks. Each block serves a generic I/O function and could be programmed to be a T1 interface, an Ethernet medium access control (MAC) block, a high-level data link control (HDLC) engine or any of a variety of protocol-specific ports. Nothing is implemented physically and independently except the external physical-layer transceivers, with functions such as Sonet framing and ATM cell delineation implemented as soft-programmed tasks in the serial data processors within the channel processors.
Unlike controllers with generic hardwired HDLC blocks, the C-Port channel processors consist of a 32-bit proprietary RISC core that can be programmed in C or C++, and serial data processor blocks for transmit and receive chains. The serial blocks take care of the mundane near-real-time packet-processing functions necessary in each packet queue, such as header field parsing, cyclic redundancy checks and checksum validations. The RISC core on each channel processor takes care of policy enforcement and traffic scheduling, providing Layers 4 through 7 prioritizing for data packets independently on each channel.
The channel processors on the chip can be aggregated in two ways. Each channel processor has a bandwidth of 300 Mbits/second, sufficient for an OC-3 (155-Mbit/s) or fast Ethernet link. When more bandwidth is required for one channel, the channel processors can be aggregated in parallel clusters, with the same software calls being associated with a higher-bandwidth channel. Channel processors also can be cascaded for pipelined processing of packets in a single data stream.
The channel processors communicate across an internal 60-Gbit/s triple bus to five separate coprocessors on-chip that perform system-wide tasks for the channel-specific I/O blocks. The five centralized units handle executive-level processing, fabric processing, table lookups, queue management and buffer management. The 60-Gbit bus is divided into separate channels for payload movement, interprocessor communications and a ring-like time-division multiplexer for table lookups.
The architecture bears some resemblance to the three-pronged bus in the StrataSwitch, from Broadcom Corp.'s Maverick Networks acquisition (see related story, page 43). But C-Port president Laurence Walker called any comparison between a LAN-oriented 9-Gbit bus and C-Port's 60-Gbit bus "pure piffle."
Husak noted that C-Port's "60-Gbit figure does not include any instruction fetch; it's a figure representing interblock communication speeds only."
The on-chip fabric processor points to the dual role the C-5 can play. Since the fabric I/O is 5 Gbits/s, the chip itself can implement a 5-Gbit switching backplane, or two chips can be combined to yield a 10-Gbit switching infrastructure. Future members of C-Port's digital communications processor family will extend the top speed of the fabric. But for powering larger switching fabrics with the current C-5, the company can link its processor directly to physical-layer switches from Power X Ltd. and other vendors. Indeed, Walker said, the company emphasized membership in the CSIX (Common Switch Interface) coalition launched by Power X and Xaqti Corp. to ensure that its microprocessors would be able to interface with a wide variety of expandable switching fabrics.
Another critical processor is the table lookup unit, which performs many of the roles of a list-processing search engine. That application is becoming a critical differentiator for many in the industry.
MMC Networks Inc. last week signed a development deal with Lara Technology Inc. for access to Lara's SuperCAM content-addressable memory search engines. And sources said that the upcoming ActiveFlow processors, from Vitesse Semiconductor subsidiary Xaqti Corp., will use pipelined search engines in conjunction with header processors for such functions as Internet Protocol differentiated services.
Various algorithms
C-Port's table lookup unit can be soft-configured for a variety of table algorithms often implemented in CAMs or SRAMs, such as longest-prefix-match searches or secure hash algorithms. One TLU can handle multiple lookup algorithms simultaneously, for advanced Layer 3 and 4 processing requiring multi-dimensional header analysis. The TLU can handle up to 133 million lookups per second, or more than 50 million IPv4 lookups per second, exceeding IPv4 packet-stream rates in OC-192 (10-Gbit) channels.
The final two processors on-chip, the queue manager and buffer manager, optimize packet throughput by fine-tuning scheduling algorithms for the packet traffic in the application and by storing packet payloads according to the buffering rules of the switching system. The queue manager offers two modes: one with a standard internal scheduling method, and a special external access mode to let OEMs supplement firmware support for advanced queuing.
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