Altern8 - Re: "Intel and SOFTCOM acquisition"
Here is the press release.
Below that, I am including a detailed article concerning SOFTCOM's technology - their programmable architecture for network packet analysis and switching/routing.
Perhaps Intel will use SOFTCOM's products as the foundation for their Network Processor !
This may be a VERY SMART move for Intel - essentially buying the technology to put them instantaneously into the Network Processor business, as opposed to "rolling their own" from scratch which would take considerable time AND RISK, all the while giving competitors like SOFTCOM (and possibly Silicon Spice) a chance to corner the market and set alternative STANDARDS.
Paul
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Wednesday July 7, 5:09 pm Eastern Time
Company Press Release
Intel to Acquire Softcom
SANTA CLARA, Calif.--(BUSINESS WIRE)--July 7, 1999--Intel Corporation today announced it has entered into a definitive agreement to acquire privately held Softcom Microsystems, Inc. in an all cash transaction.
Softcom develops and markets semiconductor products for original equipment manufacturers (OEMs) in the networking and communications market segments. The company's high performance components are designed for networking gear (access devices, routers, and switches) used to direct voice and data across the Internet as well as traditional enterprise networks. Softcom products process packets of information within high-speed networks based on the Asynchronous Transfer Mode (ATM) and Synchronous Optical Network (SONET) protocols.
Tony Stelliga, president & CEO of Softcom, will continue as general manager of Softcom, reporting to Mark Christensen, vice president and general manager of Intel's Network Communications Group. In addition, all Softcom employees will become employees of a subsidiary of Intel.
Intel, the world's largest chip maker, is also a leading manufacturer of computer, networking, and communications products. Additional information is available at www.intel.com/pressroom.
Softcom, founded in 1996, is privately held and venture backed by Sequoia Capital, Sevin Rosen Funds, US Trust Company of New York, Orion Capital and Star Ventures. For more information on Softcom, visit Softcom's website: www.softcom-micro.com.
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Contact:
Intel Corporation
Jessica Daughetee, 503/264-1216 (Trade Press)
jessica.daughetee@intel.com
Tom Beermann, 408/765-6855 (Business Press)
tom.beermann@intel.com
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More Quotes and News: Intel Corp (Nasdaq:INTC - news)
Related News Categories: computers, semiconductors
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eet.com
Posted: 11:45 p.m., EDT, 7/10/98
Startup could redefine network-processor silicon
By Loring Wirbel
FREMONT, Calif. — A small semiconductor startup here has demonstrated a microprocessor concept that could do an end-run around the debate between microprogrammable RISC engines and hardwired packet processors as vehicles for moving ATM and Internet Protocol packets at gigabit speeds.
The state-machine architecture that Softcom Microsystems Inc. unveiled at the kickoff of the GigNet show in Boston performs generic analysis on packet headers, but relies on a separate BIOS to download information about the type of packet parsing to be done. The technology could ultimately serve a variety of systems — from asynchronous transfer mode (ATM) switches to terabit routers.
The company has many rivers to cross before its SoftcomEngine displaces RISC chips and DSPs from the likes of Motorola Inc. and Texas Instruments Inc., or ASICs crafted by large networking OEMs. But Softcom — founded by developers from Fore Systems, LSI Logic, MicroUnity and PMC-Sierra — already has won venture backing from Sevin-Rosen and Sequoia Capital and accolades from companies as diverse as Intel Corp. and XLNT Designs Inc.
Frank Dzubeck, president of market-analysis firm Communication Network Associates (Washington), predicted that Softcom will be the the first among many to devise partitioned Layer 3 processors. He said another startup based in New England may be fairly close to announcing a similar scheme.
"The intent here is to create a new class of 'mass-customization' in the switching-chip industry," Dzubeck said. "Softcom is saying they can offload the dirty work for high-layer packet tasks by treating the underlying switching fabric as irrelevant. Existing switch manufacturers might not want to go that route, because it assumes the switch itself will be dumber."
The centerpiece of Softcom's strategy is the standalone SoftcomEngine processor, implemented in native 64-bit mode with a 128-bit version to follow next year. The company also has defined a PCI card with multiple port types, making it possible to instantly upgrade frame or ATM switches, backbone routers and even digital subscriber line access multiplexers, or DSLAMs, to support faster packet forwarding.
Because the 128-bit version of the processor will have dual OC-48 (2.5-Gbit) Sonet ports, second-generation devices could find a home in terarouters with wavelength-division multiplexing interfaces.
Softcom's chief executive officer, Tony Stelliga — who founded the company in 1996 after stints at Newbridge Networks, LSI Logic and MicroUnity — said the approach to partitioning packet-processing duties differs from any of the switch-controller or address-resolution logic devices promoted to date. The first step in defining the engine lay in abandoning data-path architectures completely in favor of a randomized state machine, he said.
The next step was to embed hardwired support for packet-header analysis in the processor itself, but with a different partitioning than the optimized architectures such as Galileo Technology Inc.'s GalNet-II for Ethernet/ IP or Maker Communications Inc.'s ATM-specific processors. Softcom uses generic header-analysis logic that operates on the first 64 bytes of a packet, in any portion of a header bit field.
The specific issue of whether ATM traffic management, IP Differentiated Services or other proprietary packet-forwarding concepts are used is relegated to a special BIOS — Softcom calls it Flame, for "flexible application module" — that's implemented as a flash-loadable reconfigurable FPGA.
making the Layer 3 processing of packets hardwired, but reconfigurable through a system BIOS, Softcom has leapfrogged the hardwiring debate of most wire-speed packet processor companies. David Passmore, research director at analysis company NetReference Inc., said Softcom appears to have solved the "impedance mismatch" between broadband backbones and baseband enterprise routers and switches.
Softcom will work with middleware protocol-stack companies to provide signaling and emulation stacks for different environments. Harris & Jeffries Inc. (Dedham, Mass.) has become its first partner by licensing its ATM LAN-emulation and signaling software to Softcom for the system-level architecture called GigaBlade.
Softcom hardware developers used a variety of tricks to embed as much descriptor-table lookup on the processor chip as possible. In some instances, a bit-map compressor was used to allow efficient table lookups for addresses and traffic descriptors.
"Caching descriptors became a key goal in design," Stelliga said. "Where you really get burned in trying to do line-rate processing is when you go off-chip to fetch something."
Softcom is touting a new metric it calls IP Hops (Internet Protocol hardware operations per second), and claims a figure of 100 to 300 IP Hops (50 per packet) for a 10-million-transistor, 64-bit processor. The company expects that to rise to 500 million IP Hops for a 100-million-transistor, 128-bit processor.
Critics may point out that the IP Hops metric gives low numbers to companies with software-programmed packet processing, such as MMC Networks Inc., Motorola and TI. But Stelliga said that by shifting from the move-and-store operations of integer processors and the Boolean operations and register shifts of DSPs, Softcom has defined a new type of processor characterized by parsing and replacement operations.
Since it's clearly tough for a startup to tout new microprocessor architectures to the internetworking OEM community, Softcom is launching chip sets along with the GigaBlade module card and a high-level application programming interface to its BladeRunner software stack.
GigaBlade is a 3U-sized PCI card with three types of interfaces from the SoftcomEngine: a Utopia-2 interface for ATM and Sonet connections, capable of handling four ports of 155-Mbit speeds; a LAN/WAN feeder interface based on a 66-MHz PCI bus; and a local memory interface for access to on-board content-addressable memory and SRAM. Independently, Softcom has defined a Gigabit Ethernet interface that can be used as a packet port for system designs that do not use PCI internally, though Stelliga said non-PCI systems are becoming a minority.
"The old-age semiconductor thinkers would say we're competing with our customers by offering boards," Stelliga said. "But since our system relies on a packet processor, the Flame BIOS and a management processor, we find that most router and switch vendors would rather have a GigaBlade deliverable for time-to-market issues."
The BladeRunner software stack lends a hand with signaling and emulation functions, while directly handling packet encapsulation in hardware. The Softcom engine has 10 separate modes of packet parsing, and can handle up to 16 types of customer-specified packet encapsulation. Even before the completion of the Internet Engineering Task Force's DiffServ standard for packet prioritization, the processor can handle all forms of Layer 2 virtual LAN creation, including 802.1p/Q. It is capable of handling any high-level application that relies on stateful inspections of a packet header, such as security, firewall filtering or encryption.
A RISC host in the GigaBlade board arbitrates between the packet snooper and the Flame BIOS over the internal C-bus, but no RISC processor is inserted into the data path of any packet transaction.
Over time, Softcom expects to become a traditional semiconductor supplier by offering its engine along with the code for Flame interfaces and the third-party software stacks. But Stelliga said more than half of the customers may choose to remain permanent board-level users of the GigaBlade. The card runs under the Wind River VxWorks real-time operating system.
Stelliga said he expects some would-be competitors, but pointed out that DSP and RISC traditionalists have a vested interest in wanting to see embedded cores within their switching-chip designs.
Indeed, analyst Dzubeck said the advent of the Softcom scheme does not mean the end of architectures like a TI ThunderSwitch with embedded 320C6X DSP, or the Galileo GalNet-II. For switches in the 10/100-Mbit space, it makes more sense to include switching and packet analysis on one piece of silicon. But as speeds reach multi-gigabit realms, it becomes necessary to segment packet processing on separate devices from switching chips, Dzubeck said.
Meanwhile, networking OEMs with internal packet-analysis ASIC teams either try to absorb escalating costs of ASIC design, like Cisco Systems with its Skystone and Granite Systems groups; or license intellectual property, such as Packet Engines Inc. with its MAC and address-resolution designs.
"Both groups will be slowed in challenging this [Softcom] architecture directly," Stelliga said.
Softcom will introduce various instruction widths of its processors, with shrinks in each version allowing for additional ports. The SCE-64I, rated at 80 million IP Hops and handling four OC-3 or a single OC-12 port, will be followed by a shrunk SCE-64is version with dual OC-12 ports. The 128-bit SCE-128v device, which boasts 240 million IP Hops, is slated for introduction in early 1999. It will handle a single OC-48 port, while the process shrink, SCE-128vs, will handle dual 2.5-Gbit ports.
Softcom is shipping OC-3 line cards to customers this summer for $1,495, and OC-12 cards for $2,495. Its Internetworking Development, Evaluation and Application boxed platform runs $15,000. The company is shooting for volume prices between $25 and $200 for its SoftcomEngine chips. |
