To: Patriarch who wrote (4544 ) 7/11/1999 4:25:00 PM From: Patriarch Respond to of 6180
TI Introduces New Military Motor Control DSP with On-Chip Flash Memory SHERMAN, TX (July 1999) -- A new military digital signal processor (DSP), the first QML compliant device designed specifically to improve system performance, lower system cost, and reduce component count in digital motor and motion control (DMC) systems was announced by Texas Instruments Military Semiconductors. The device is built around a TI 'C2000 programmable TMS320 DSP core, enabling the use of modern control algorithms that support a motor- industry trend towards improved control of economical brushless motors in a broad range of products. The SMJ320F240HFPM40 is fully QML qualified and is packaged in a 132-pin ceramic quad flatpack. DSP Solution Optimized for Digital Motor Control The new SMJ320F240 DSP uses TI's 320C2xLP 16-bit, fixed-point DSP core and integrates a motor-control event manager whose features allow the device to control electronically commutated motors in the most optimal fashion. The device leverages TI's reusable DSP core technology and demonstrates TI's capability to produce application-targeted DSP solutions through integration of a DSP core along with digital and mixed-signal peripherals on a single chip. As the first QML compliant DSP optimized for digital motor control, the 'F240 supports motor commutation, command generation, control algorithm processing, data communications, and system monitoring functions. The combination of a DSP core, the motor-control-optimized event manager, and on-chip analog-to-digital converters (ADC) all working together provides a single-chip digital control solution for motor drive designs. The 'F240 includes a 20-MIPS DSP core, the event manager, two serial interfaces, a pair of 10-bit ADC, 32 bits of digital input/output (I/O), a watchdog timer, and 16K words of flash memory. Event Manager, DSP Core Change System Design Approach DSP-based electronic motor drive systems enable variable-speed direct drive of inexpensive brushless motors, eliminating or reducing the need for belts, gears, sensors, hydraulics, pulleys, and counterweights. The processing power of the 'F240 enables more robust system performance through the use of modern intelligent and adaptive control algorithms. These allow a motor to run at precisely the necessary speeds, while adapting to loading, temperature, and other parameters. This improves the motor's energy efficiency and reliability, reduces noise by improving torque ripple, and lowers system cost by reducing parts count and maintenance costs. The 'F240's integrated event manager uniquely positions the device as an optimized DSP solution for digital motor control. The event manager supports up to 12 pulse-width modulation (PWM) outputs with PWM and I/O features that include three timers, nine comparators, dead-band generation logic, and a state-space vector PWM generator. In the event manager, there are also four capture inputs, two of which can serve as direct inputs for optical-encoder quadrature pulses. Dual on-chip, 10-bit ADC provides precise conversion of information such as current or voltage feedback. All these features help the 'F240 reduce component count, power consumption, vibration, and noise. Migration Path Through Compatibility The SMJ320F240 is object code compatible with the 320C2xx generation and is upwardly compatible with the 320C5x generation. The device leverages 'C2000 fixed-point DSP software development tools and JTAG emulation support to allow the developer to easily migrate motor-control applications from microcontrollers to the new DSP. The SMJ320F240HFPM40 can now be ordered under the SMD# 5962-9861201QXA and is priced at $125.89 in production volumes of 100 units. This part is also available as a military temperature device. # # #