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To: Tenchusatsu who wrote (85108)	7/8/1999 1:32:00 PM
From: d[-_-]b	Respond to of 186894

Ten, I understood the first time, I wouldn't use the box for a server either. However, folks buy under powered toy pickups to haul stuff - don't they.

To: Tenchusatsu who wrote (85108)	7/9/1999 11:30:00 AM
From: Proud_Infidel	Respond to of 186894

eetimes.com Intel, Hitachi back stacked chip-scale package By Yoshiko Hara EE Times (07/08/99, 6:24 p.m. EDT) TOKYO — In an effort to establish a de-facto packaging format for chips used in the rapidly growing cellular-phone market, Sharp Corp. has signed on Intel Corp. and Hitachi Ltd. as the supporters of its stacked chip-scale package (CSP). Their move follows Mitsubishi Electric Corp.'s decision last September to use the same packaging format. The group is targeting the same market as a separate group backing a different package, called the stacked Multi-Chip Package, that will hold the same combination of memory devices — flash and SRAM — for mobile systems. "Now that the stacked CSP specifications involve Intel and Hitachi, we can be a second source to each other to guarantee users with secured supply," a Sharp spokesman said. Intel announced a flash-plus-SRAM device last May that was compliant with the CSP specification, and has started selling samples of that part. Volume production will begin in the second half of this year. Hitachi agreed to adhere to the specifications of the stacked CSP group and is now considering their application, a Hitachi spokesman said. Hitachi has been collaborating with Mitsubishi in flash memory, which is one reason it elected to join the group, said the spokesman. When Hitachi introduces its CSP chip, it will be a DINOR flash and SRAM combination. Mitsubishi has developed DINOR structure flash memory for small capacity, fast speed applications. The group of companies will use the same package size, pin assignments, ball layout and pitch, and basic commands for flash memory to guarantee pin-compatibility. The package size is 8 x 8 mm, 8 x 10 mm, 8 x 11 mm or 8 x 12 mm with height at maximum 1.4 mm. The standard specifies 64-pin and 72-pin packages with a pin-pitch of 0.8 mm. The combination of flash memory for data storage and SRAM for work memory is used for portable products such as cellular phones and personal information tools. Demand for such devices is growing rapidly with the increase in sales of mobile products. There are two competing standards groups in the arena of stacked combinations of SRAM and flash memory. One group is headed by Sharp, and now includes Mitsubishi, Intel and Hitachi. Sanyo Electric Co. Ltd. and Seiko Epson Corp. have also expressed their support of this format. In opposition to that alliance, Fujitsu Ltd., Toshiba Corp. and NEC Corp. agreed last September to follow specifications for the stacked Multi-Chip Package (MCP), which holds the same combination of memory devices. The trio made a pin assignment of SRAM die compatible with that of the flash memory, which allows stacking with minimal wiring. The common specifications are for a BGA-type configuration with 8 x 8 metal balls or 56 balls (excluding dummy balls). Hyundai Electronics Industries Co. Ltd. and Samsung Electronics Co. Ltd. have also endorsed the MCP specification. Seiko Epson has endorsed both groups, saying that the company intends to be ready for both specifications to satisfy its customers. The target of each group is the same. With multiple adherents to the respective specifications, users can have the same pin layout on a printed-circuit board and buy from multiple second sources, while suppliers can collaborate to promote the stacked CSP or MCP as a de-facto standard.