BK,
To save you the effort of reposting, and to save me the effort of reading things twice, I've just posted this directly to the AMAT thread... ;-)
Ian.
+++++++++++++++++++
A good article on Process Tools from the July SemiBizNews
supersite.net
Can more expensive tools keep driving down fab costs?
Talk about sticker shock! Purchase prices of new wafer-processing tools continue to go through the roof as the pace of technology accelerates in wafer fabs. If the cost of putting up a state-of-the-art wafer-processing plant hits $10 billion during the next decade, as some experts predict, tool inflation will be the driving force.
"This is a major concern for the whole industry because costs are escalating every year," declares Bill Walker, senior vice president of manufacturing at Motorola Inc.'s Semiconductor Products Sector in Austin. "The biggest cost is the equipment set. You can do things to utilities, water, and other aspects [of running a fab], but they are all fairly small pieces of the total cost when compared to depreciation of the overall tool set."
Some chip makers aren't impressed with the efforts of tool suppliers to hold down costs and improve overall equipment effectiveness (OEE), which covers throughput, uptime, and reliability. "I think the users of some pieces of equipment have been taken to the cleaners, and it's about time we let the suppliers know," complains Paul Murphy, vice president of worldwide wafer manufacturing at National Semiconductor Corp. in Santa Clara, Calif.
One of the biggest problems now with fab gear is that new generations of tools often are built on completely new platforms, he points out. The equipment suppliers "have to get smarter and build subsequent tools on existing platforms so that they can leverage learning," Murphy says. "They don't have to double the price of a new tools everything one is introduced," he complains.
Murphy also is unhappy with the reliability of current tools. "My Honda can go for five years without a major failure and [the chip gear vendors'] darn equipment should be able to go 500 or 1,000 hours without failure too," he declares. "Some suppliers said it couldn't be done, but we have proven to them in many cases it can."
But Murphy is critical of chip makers too. "We've all done a pretty miserable job of squeezing the last ounce out of our tools," acknowledges the 25-year industry veteran. He says too many times in the past, semiconductor fabs would rush out to buy another system, once their equipment began "operating at a mediocre level."
The chip-making gear fanning the flames of tool inflation the most these days is photolithography (see "Chip makers gripe bitterly, but litho costs keep soaring" ). But nearly all types of equipment are sharply driving up capital costs in chip factories.
The price of leading-edge etchers, for example, have jumped from about $1 million each to more than $2.5 million since the mid-1990s. New types of tools, such as chemical mechanical polishing (CMP), and factorywide automation systems also are pushing fab budgets higher. Even the cost of wet benches for wafer cleaning are expected to nearly double from a little over $1 million each to $2.5 million or more when 300-mm wafers move into volume production.
Equipment suppliers maintain there are plenty of good reasons why cutting-edge tools are getting more expensive. Device shrinks, larger 300-mm wafers, new materials, more automation, and the need for embedded process-monitoring systems are all responsible for higher prices. Pricetags are up by as much as 50-to-100% over the previous generation of hardware.
But along with these higher price tags comes higher productivity, industry officials insist. The new-generation tool sets are expected to boost productivity significantly by processing higher volumes of silicon each day, eliminating costly mistakes, detecting equipment failures before they happen, and even eliminating the need for other types of systems at the end of the production line.
"Across the board, process tools - including etch, deposition, and other systems - as well as those for inspection and metrology, will continue to become more expensive for a couple of good reasons," says Ronald Dornseif, the analyst tracking wafer-processing technology at Dataquest in San Jose. "First, the process technologies are getting much more difficult, sophisticated, and complex."
"But second," he says, "the IC companies are continuing to migrate 'value' to the tool supplier - meaning they are pushing their expenses on to the supplier community." Expenses that formerly were internal charges covering the cost of R&D by the chip maker are now covered instead in the selling price of the production equipment as more system vendors develop the process technologies and integrated tool sets, Dornseif says. "This means that ongoing expense is coming back to the chip companies as an capital expense," he adds.
Suppliers are quick to add they also are working hard to reduce the rising costs from fab operations and improve overall productivity by increasing equipment throughput, reducing the amount of cleanroom space required for process steps, integrating more functions into clusters or single pieces of gear, and boosting flexibility of tools that shorten fabrication cycle times. At the same time, equipment makers are facing a great deal of uncertainty as chip making makes major transitions to larger wafer diameters and new semiconductor materials such as copper interconnects and dielectrics for both low-k and high-k applications.
"The biggest area of change is in the backend of the line for logic, where copper damascene and low-k materials are creating a paradigm shift," points out Greg Campbell, vice president and general manager of the Etch Products Business Group at Lam Research Corp. in Fremont, Calif.
With the industry split between organic and inorganic dielectric materials, tool suppliers are still having to cover a wide range of candidates in their efforts to hone next-generation processes and equipment. "I think the material transitions need to settle down before the wafer-size transition can pick up full momentum," Campbell says.
Process steps, tool usage, and costs in the back-end-of-line (BEOL) for chip interconnects have mushroomed when compared to the expenses in the front-end-of-line (FEOL) processes that are used to build transistor structures. Since the early '80s, the number of steps to produce an CMOS integrated circuit has grown from about 100 process steps to a total of 300, estimates Rinn Cleavelin, director of the Front End Processes Division at Sematech in Austin, Tex. Today, only one-third of the process steps are used to make transistors in the FEOL portion of a fab, down from as high as 60% in the early 1980s, he figures.
But there are major questions ahead in the FEOL processes. One of them concerns the materials that will be needed to replace silicon-dioxide in gate structures. And "there's a real question mark about whether we can scale materials [in the gate stack] below 10 angstroms," Cleavelin adds, referring the industry's ability to continue device shrinks in 10 years. "It will get real interesting," he believes.
While researchers look for new ways to keep device shrinks going, which is currently the No. 1 tool for keeping on the cost/performance curve of Moore's law, the industry is investing heavily in R&D on the BEOL side of wafer processing to control the cost and performance of interconnects. The growing cost of lithography absolutely is chewing up budgets in interconnect processes, notes Ken Monnig, associate director of Sematech's Interconnect Division.
"People complain about the cost of individual processes - like CMP being one of the biggest targets today - but it still pales in comparison to the projected increases in lithography," Monnig warns.
Tool and process-step integration have become key weapons in the battle to curb today's growth in fab costs, and many equipment suppliers expect to continue those strategies into the next decade. The bundling of process steps not only is expected to cut development costs and time for chip makers but also is being counted on to speed the ramp up of volume production in new frontend lines, say equipment suppliers. With today's cleanroom space costing as much as $3,000 a square foot, equipment integration enables chip makers to pack more production capabilities in less fab space.
For example, integrating post-CMP cleaning systems with wafer polishers can save 30% of the floor space formerly needed for these jobs, says Willy Krusell, vice president and general manager of Lam's CMP/Clean Products Business Group in Fremont, Calif. Other CMP suppliers also are aiming to integrate more functions with their tools as well. For example, Applied Materials Inc. sees major savings potential in integrating not only the wafer cleaning step with CMP polishers but also with greater levels of metrology.
"Some wafer fabs are now spending up to 50% of the time in CMP processing sections monitoring wafers," points out Rob Davenport, director of Applied's CMP division in Santa Clara, Calif. The creation of new in situ metrology features and monitoring capabilities will not only eliminate the need for support systems in CMP processes, but also will "make possible adjustments on the fly in critical tools," he adds.
Another trend that's driving up the price of individual tools, but which is also adding higher levels of control and flexibility is the move from batch to single-wafer processing, say many equipment suppliers. Some single-wafer tools, such as rapid-thermal processing (RTP) systems, are not only working on one substrate at a time but they alsoare beginning to do it so fast that they're rivaling batch systems in total throughput.
"One major issue for fabs is reducing the time it takes to get products through the factory," explains Brad Mattson, CEO of Mattson Technology Inc. in Fremont, Calif. "One way to do that is with raw speed and the other is with cycle time. Single-wafer processing greatly improves the cycle time in fabs when you no longer have to accumulate hundreds of wafers for batch furnaces or wet benches."
Single-wafer processing architectures have helped some equipment makers create new "bridge tool" platforms capable of handling today' 200-mm wafers but also able to process 300-mm substrates when they move into production. This strategy is aimed at sharing costs between new 200-mm processes and the initial 300-mm tool set while equipment suppliers wait for chip makers to make the transition to larger wafer diameters.
"The cost of 300-mm wafers will be monumental and that will drive you to single-wafer processing through out the fab," predicts Richard A. Aurelio, CEO of Varian Semiconductor Equipment Associates Inc. in Gloucester, Mass., which moved to a single-wafer platform for its ion implanters six years ago. "Single-wafer processing will allow you to work with smaller batch sizes [of IC designs], which will be essential for silicon foundry operations," he maintains.
But not everyone agrees. In fact, engineers at Eaton Corp.'s Semiconductor Equipment Operation believe that more expensive batch-wafer implanters can end up saving money in medium-current applications as future devices require a series of "chained" implants. Consequently, Eaton modified its high-energy ion implanter platform to perform medium-current implants for well engineering and voltage threshold adjustments on 13 eight-inch wafers at a time.
This new system will sell for about $3 million, which is about $1 million more than single-wafer medium-current implanters. But typical fabs will need just two of these implanters vs. four of the single-wafer implanters because of the higher total throughput in chained implants. That will save a fab $2 million in equipment purchases up front, estimates, Mary Puma, vice president of the Eaton operation in Beverly, Mass.
In the wafer cleaning steps, a growing number of equipment suppliers also are attacking costs with single-wafer processing technologies and tool designs. GaSonics International Corp. in June launched a new single-wafer cleaning system that uses dry plasma technology to remove photoresist and etch residues. This eliminates the need for a 60-foot-long wet tank, the company says.
"This process frees up a lot of space and reduces the need to buy a lot of chemicals and consume huge amounts of water," says Ken Drachnik, general manager for the ash business unit of GaSonics in San Jose. "This is part of our efforts in integrated clean technology."
Suppliers of wet-cleaning systems also are looking for ways to cut operational costs by reducing the use of chemicals, eliminating solvents, and speeding wafer throughput rates. SEZ Group in Villach, Austria, has taken a new approach to wet-cleaning by offering a spin-processor platform that performs single-wafer cleaning with less chemistry and in less floor space, claims Wolfgang Krammer, executive vice president for the company's SEZ America Inc. subsidiary in Phoenix.
"On the tool side [of cleaning], we are going to be looking at using more in situ process control for end-point detection systems and scheduling preventative maintenance," he explains. SEZ is attempting to compete with batch wet benches that handle 100 to 250 wafers in an hour. "We have repackaged our technology to do 150 wafers an hour at a competitive price with standard wet benches," claims Michael West, business and strategic technology director at SEZ America.
Other vendors are coming with cleaning systems that attack the cost of wet processes by reducing and diluting chemistries and moving to tools with simpler processes. Fab managers also are able to reduce some of their wafer cleaning steps because cleanrooms, equipment, and chemicals are all getting cleaner, says Dana Scranton, director of marketing for the Surface Preparation Division of Semitool Inc. in Kalispell, Mont.
Certain cleaning steps are less likely to be needed in the future, Scranton notes, "so fabs will be able to use alternative cleans with reduced steps, reduced concentrations, and reduced time." Semitool is delivering a cleaning system with a solvent-free cleaning application that lowers the cost of disposing spent chemicals.
Waste prevention of another sort is the target too of new metrology and inspection systems, which are moving into the fab to provide real-time feedback on processes and tools. New in-line "nanometrology" tools, such as atomic force microscopy (AFM) and focused ion beam (FIB) tools are making their way from analytical labs into the fab. Analysts expect these types of tools to increase in fabs during the next decade (see story in the Feb. 15 publication).
For example, FEI Co. is offering a three-dimensional measurement tool that combines FIB with scanning-electron microscopy (SEM) to give fab workers instant images of device and interconnect profiles on deep-submicron ICs. Most fabs have had to use outside labs to perform that type of analysis - a process that can take weeks.
"The payback time could be just days [if processes are out of control and fabs don't know it]," says Jay Lindquist, vice president of marketing for FEI's Microelectronics Products unit in Hillsboro, Ore. "The biggest issue now is getting the word out that this technology can be used [in the fab after being] established in the laboratories for a long time."
A similar effort also is underway at Philips Analytical, the Dutch-based subsidiary of Royal Philips Electronics N.V. At the Semicon West in July, the company plans to show what it says will be the industry's first in-line process control tool for metal interconnects. The Philips Qualifier series measures thin films by combining ultrasonic waves and laser exposures. This system will enable fabs to look at the metal interconnect in each layer and rework wiring before it is covered by subsequent process steps.
"One of the things that's so striking in today's wafer fabs is the general lack of in-line metrology," says Alec Reader, semiconductor marketing director and vice president of Philips Analytical. "It would be unthinkable for General Motors to push their products through manufacturing lines without systematic checks, and yet many fabs are going off-line to do their failure analysis," he notes. -- J. Robert Lineback |
