Amy and Thread,
This doesn't appear to have been posted. Thinking long-term here.
From the June 22, 1999 issue of PC Magazine Online:
zdnet.com
Barry
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Moore's Law Will Continue to Drive Computing
Computing power has increased at an amazing--and amazingly consistent--pace. New technologies promise more of the same in the future.
By Nick Stam
In 1965, Intel Corp. cofounder Gordon Moore predicted that the density of transistors in an integrated circuit would double every year. His axiom, dubbed Moore's Law, was later changed to reflect 18 months' progress. Moore's Law has proven remarkably accurate for over three decades. Not only transistor density but also microprocessor performance tends to follow Moore's Law.
Andy Grove, former Intel CEO and chairman, predicted at Fall Comdex 1996 that by the year 2011, Intel will ship a microprocessor with 1 billion transistors, operating at 10 GHz, using a 0.07-micron semiconductor process technology able to calculate 100 billion operations per second. If we extrapolate out to 2011 starting from a Pentium III in early 1999 at 9.5 million transistors (for its core logic and L1 cache), Moore's Law would indicate around 2 billion transistors per chip by 2011, which is double Grove's estimation.
Microprocessor Report's founder and executive editor, Michael Slater, thinks that in the future, doubling transistor count may require more than 18 months when moving from one major chip design or fabrication technology to the next. This is due both to more complicated chip logic (requiring longer design and validation time frames) and to increasingly difficult hurdles in chip fabrication technology.
Fabrication technology must improve in many areas with each successive process generation, such as the current move from 0.25-micron design to 0.18. One particularly critical process is photolithography, whereby short-wavelength light sources are focused with a number of precision lenses and shone through small transparent masks containing circuit details. This exposes the photoresist on a wafer's surface, which is chemically removed leaving microscopic details of the circuit pattern on the wafer. Then dopants, such as boron or phosphorous, are implanted to alter electrical characteristics, with multiple iterations of these processes and others required to form all active devices.
Light sources and optics must evolve in concert, according to Mark Bohr, Intel's director of process architecture and integration technology and an Intel Fellow. Later this year, Intel will ship 0.18-micron Pentium III chips using the same 248-nm wavelength deep-UV light source used in current 0.25-micron Pentium II and Pentium III chips. But when moving to 0.13-micron processes three or four years from now, expect to see 193-nm wavelengths using excimer lasers as the light source.
Beyond 0.13- could be a 0.09-micron process, which would use 157-nm wavelength excimer lasers, according to Bohr. And the next step below 0.09 is a big one in terms of technology and manufacturing processes: the 0.07-micron process used in Grove's processor of 2011.
This level of photolithography will likely require extreme-UV (EUV) light sources. EUV has a wavelength of only 13nm, which has long-term potential for etching far smaller transistors, but is confounded by the current lack of known transparent-mask materials that will allow such short wavelengths to pass through. This requires entirely new reflective lithography processes and optics to be implemented coincident with EUV.
As you continue to increase the number of transistors over time, transistor interconnect wires get smaller and closer together, increasing resistance and capacitance while adding to circuit delays. To reduce resistance and shrink interconnect line widths at the smaller dimensions, copper will displace aluminum as the interconnect metal of choice, as seen in the new IBM PowerPC G3 chips. AMD's CTO, Atiq Raza, predicts AMD's new chips will be in copper by the second quarter of 1999. Bohr expects that future Intel CPUs in the 0.13-micron process and beyond will use copper interconnects. Update: AMD's CTO, Atiq Raza, predicts AMD's new chips will be in copper by the second quarter of 2000, not 1999 as is reported
In what many consider an important chip fabrication breakthrough, IBM has developed Silicon on Insulator (SOI) technology to reduce the capacitance of transistors, with claimed speedups of about 25 to 30 percent. With SOI technology, transistors are built on top of a thin film of silicon, which is atop a layer of silicon dioxide. IBM states that the performance gain is about the same as would be seen in a two-year period with normal process improvements.
Another SOI advantage is that it lets transistors operate with lower voltages, which also benefits wireless devices and portable devices. AMD's Raza also thinks SOI is a significant advance, and that we'll see it in many chips beyond PowerPCs in the next few years. Intel's Bohr thinks SOI does have performance advantages, though more likely only a 15 percent improvement, but that its higher manufacturing costs and more design complications may make SOI less attractive than other performance-improving techniques.
Power and heat management could pose huge problems in the future. As transistors continue to shrink, their gate oxides must become only a few molecules thick to maintain required transistor switching speeds, and low voltages will be necessary to maintain their structural integrity. Intel has stated that chips ten years from now will operate at less than 1 volt and could easily consume 40 to 50 watts of power, which implies 50-amp or larger currents. Evenly distributing such huge amounts of current within the chip and dissipating the tremendous amount of heat generated are both subjects of much research.
Will current silicon fabrication methods hit physical limits by the year 2017 (as many have predicted), meaning that we'll reach a point where we just won't be able to build usable transistors any smaller? It's difficult to look that far ahead, but research into areas such as molecular nanotechnology, optical or photonic computing, quantum computing, DNA computing, chaotic computing, and other seemingly esoteric areas of research may prove fruitful, changing totally the way we design and manufacture microprocessors or perform computations.
Still, there is much life left in silicon technology, and as Bohr noted, we seem to have a knack for discovering ways of extending existing technologies while developing new techniques to solve complex problems. Even if one of the esoteric research areas did prove technically feasible over the next ten years, an entire industry's infrastucture wouldn't change overnight, and such new technology could take many more years to reach volume manufacturing.
Aside from technological barriers, the rising costs of semiconductor fabrication plants could be a serious roadblock to future chip development. Today's leading-edge microprocessor fabrication plants cost around $1.5 to $3 billion, and $5 billion fabs are probably only four or five years away. With more and more devices using microprocessors, such capital investments, though staggering, may still make economic sense. But it's important for the entire semiconductor industry to make its manufacturing processes cost-effective.
Many people are promoting the need for modular, or upgradable, fabs, which would reduce the costs of moving from one process generation to the next. It's also likely we'll see more partnerships among chip vendors sharing fab development and operational costs in the future. The move from 200-mm (8-inch) wafers to 300-mm (12-inch) wafer production is also underway, with transitions expected in the next few years that will provide more chips and higher profit margins per wafer.
Not only will fabrication technologies undergo huge changes in the coming years, but so will microprocessor architectures, including in their logic designs, instruction sets, register sets, external interfaces, and on-board memory sizes. According to John Hennessy, dean of Stanford University's School of Engineering and cofounder of MIPS Computer Systems, for the past ten years we've been trying to squeeze more parallelism out of instruction streams (to take better advantage of superscalar CPU designs). He claims we are in the later stages of the quest for more instruction-level parallelism (ILP), particularly with the x86 instruction set. The transistor counts, power requirements, and design complexity required to exploit ILP incrementally, without a radical change in microarchitecture, will become increasingly painful in terms of cost and design time, says Hennessy.
We've seen various levels of x86 superscalar designs and instruction set extensions in recent years with Pentium, Pentium MMX, Pentium Pro, Pentium II, Pentium III, AMD K6-2, and K6-3, Cyrix MI and MII, 3DNow!, and Streaming SIMD Extensions. Even with the technical challenges cited by Hennessy, we'll still see more complex 32-bit x86 processors being introduced by AMD, Cyrix, Intel, and others in the coming years as well.
Enter the radical change in microarchitecture: Intel and HP introduced their EPIC (Explicitly Parallel Instruction Computing) instruction set technology, which is a total departure from x86, in October 1997. Their 64-bit, IA-64 architecture is the first instruction set to incorporate EPIC principles, and their upcoming Merced processor is the first IA-64 implementation.
Creative microarchitectural techniques are still available to enhance 32-bit x86 designs, but reaching substantially higher levels of performance requires totally new methods like EPIC, according to Fred Pollack, who is director of Intel's Microcomputer Research Lab and an Intel Fellow.
According to Pollack and John Crawford (an Intel Fellow and EPIC co-architect), EPIC compilers will look across a much larger window of instructions than possible with hardware to expose more of the ILP present in the source code. The compiler tries to find instructions in the source code stream that have no data or CPU resource dependencies. Three instructions are then grouped into a 128-bit bundle, and one or more bundles may be executed in parallel in the CPU (assuming the CPU has enough functional units to handle all the instructions concurrently). Future EPIC-based processors will most certainly have many more functional units, and compilers will likely be able to squeeze more parallelism out of the code.
EPIC also includes other key features under software control, such as speculative loads (which reduce memory latency) and predication (which remove branches). Given that the gap between CPU and memory speed continues to widen, speculative loads permit data to be loaded from memory before it's actually needed, providing a head start on the operation.
Predication permits both sides of a branch instruction (such as the THEN and ELSE blocks of an IF statement in a high-level language) to be executed concurrently, until the proper path is determined and the incorrect path is discarded. Branches that can be predicted with a high degree of accuracy by branch prediction hardware typically aren't predicated, because predication consumes more CPU resources. The net result is that predication creates more parallelism and reduces branch misprediction penalties.
EPIC-based processors should scale far into the future with various IA-64 implementations. Intel has already announced multiple generations of IA-64 processors for servers and workstations three to four years from now. The big question is whether EPIC will truly succeed, and if so, will it eventually be used in our mainstream desktop systems? And will 32-bit, x86-based processors continue to proliferate if EPIC does gain mainstream momentum?
According to Pollack, as the computer market matures it is becoming increasingly fragmented, thus Intel will continue to develop and tune processors for a variety of market segments. They are initially targeting IA-64 at workstation and server segments, and future high-end, 32-bit, x86 chips at professional and power-user markets. AMD's Raza doesn't doubt that 64-bit processing will be important for some markets five to ten years down the road, but he would not tip AMD's 64-bit hand, other than to say that AMD's working on it. He is skeptical of EPIC's success, more because of the inefficiencies of two large companies collaborating than because of the technology itself.
Raza also believes 32-bit, x86 processors have a long life and thinks they will still exist 20 years from now, due to the huge installed base of software. (If you question that statement think about the Y2K bug and all the IBM 370 architecture– ;based Assembler and Cobol programs from the seventies and early eighties that are still running key business functions of many corporations today). Both Raza and Pollack think 64-bit processing will be mainstream ten years from now, but they are hesitant to forecast 64-bit processors on all our desktops in five years' time.
There's a trend toward larger caches in today's chips, such as the Celeron, Mobile Pentium II, and AMD-K6-3. According to Keith Diefendorff, editor-in-chief of Microprocessor Report, we can expect 2MB to 4MB of cache memory built into mainstream chips over the next few years, but there reaches a point of diminishing performance benefit with existing x86 software because of limited working-set sizes (or active memory footprint). Software built with future instruction set architectures like EPIC may benefit from far more on-chip cache.
In addition to large caches, an incredibly important objective, according to AMD's Raza is to get as much fast memory as close to the processor as possible and to reduce latencies to I/O devices. This goes beyond Rambus Direct RDRAM memory and 64-bit PCI buses, or the PCI-X and NGIO advanced I/O bus initiatives. Raza claims we must design future CPU chips with far faster and more direct interactions with main memory, graphics, and especially lower bandwidth streaming devices (such as disks and communications devices).
We'll also see a trend toward System on a Chip (SOC) designs, which incorporate cache, memory control, I/O control functions, and even embedded DRAM in some cases. Mainstream notebooks (using external RAM), hand-held PCs, palm PCs, set-top boxes, and other information appliances are candidates for such devices. We expect SOC devices to reach huge volumes in selected markets over the next five years.
Another category, called chip multiprocessors (CMPs), will include multiple processor cores on a single chip and are expected to proliferate during the next decade. We'll need to see more multithreaded applications and multitasking to take advantage of these architectures. In the long term, such multiprocessing designs may delay the need to shift to exotic computer designs, if we assume silicon technology really will hit the wall around 2017. But it will take time for CMPs and complex multithreaded applications to evolve in the mainstream markets, according to Hennessy. He believes the embedded-CPU market would be the first target for CMPs. Set-top boxes, video games, and digital TVs are probable candidates. Slater believes we'll see CMPs in workstations and servers, though memory bandwidth for the multiple cores on a chip could be a big problem.
We may also see systems with 10 or 20 of Andy Grove's future chips installed, or maybe multiple billion transistor cores on a single large die for high-end computing systems. Then again, it's not difficult to imagine the need for 4, 8, or 16 processors in mainstream computers. We all want multiple intelligent agents simultaneously acquiring and processing data from external sources, and systems that understand natural language. There are numerous scenarios we could envision that would benefit from multiple processors working simultaneously.
Expect much innovation for many years to come in silicon fabrication and CPU architectures. You'll have a billion transistors on a chip by the year 2011—if not sooner—and your computing devices will be far more powerful than you can imagine. And who knows? one of the exotic technologies in research labs may suddenly gain incredible momentum and become a viable alternative in the next 10 to 20 years.
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