SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: fyo who wrote (66092)7/19/1999 2:18:00 PM
From: Ali Chen  Read Replies (1) | Respond to of 1576876
 
Fyo, < no reason NOT TO expect a CuMine with 133MHz FSB and
DRDRAM>
If I am not mistaken, there must be a special
controller to support the dual data rate DRAM.
If you are aware of corresponding Intel
chipset, please post.



To: fyo who wrote (66092)7/19/1999 2:49:00 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 1576876
 
<And when do you honestly expect AMD to come out with 2MB cache Athlons?>

When AMD announced that K7 will be able to support a maximum of 8MB L2 cache, some people thought that the 8MB K7 was not only possible, but probable. In other words, they were talking as if the K7 w/ 8MB of L2 cache was already a done deal.

I personally don't expect the L2 cache on the Athlon to grow any larger than 2MB, like Xeon. The reason isn't capability; I'm sure AMD can do it if they tried. The reason is return-on-investment. Unless Athlon has some major scalability problems with multiprocessing, I don't think they need larger L2 caches.

Tenchusatsu