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To: John Walliker who wrote (86016)7/20/1999 11:05:00 AM
From: Scumbria  Read Replies (2) | Respond to of 186894
 
John,

Perhaps they will be linked with Rambus channels?

In grad school at Rice, I worked on a distributed memory computer- where each node had it's own address space. This type of memory model would make it possible to implement one memory controller per CPU, but it would require a radical departure from the current Intel SMP architecture.

Scumbria


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