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Low-k materials not ready for prime time
By Will Wade
EE Times
(07/22/99, 1:44 p.m. EDT)
SAN FRANCISCO — While copper interconnects were the main story at last year's Semicon West, there was no follow-up at this year's recent conference from those working on copper's less-glamorous cousin: low-capacitance dielectric materials. With competing deposition technologies and several different materials seen as candidates for the low-k film, as it is generally called, a variety of system vendors and materials companies are jostling for position in the starting gate.
Most executives and analysts agree that the next generation of speedy chips will utilize both copper interconnects and low-k dielectric layers, but it remains uncertain whether a low-capacitance replacement for silicon dioxide is ready yet for prime time.
"The low-k implementation is pretty much on hold," said Dan Hutcheson, president of VLSI Research Inc. (San Jose, Calif.). "People are having a terrible time making it work."
The dielectric layer is an insulator within a chip that surrounds its interconnect wiring. Just as faster interconnect material, such as copper, allows a signal to move faster through the chip, decreasing the capacitance factor of the insulating material also allows signals to travel across the interconnect faster because they have less interference with each other. The most common dielectric material is silicon dioxide, which has a k value of 4.3. Hutcheson said that chip companies hope to find a new, low-k dielectric material they can implement with k values below 3. So far, no major chip companies have publicly demonstrated any designs that utilize low-k technology in volume, although many of them are working on the process.
There are two main approaches in the low-k effort. Traditional tool companies such as Applied Materials Inc. and Novellus Systems Inc. advocate a chemical vapor deposition (CVD) tool, which mixes basic gases in a complicated recipe of time, pressure and heat to form a layer of dielectric material that is deposited onto the wafer. That approach is very familiar to chip makers, because silicon dioxide is also applied with CVD technology.
The rival school is promoted by material companies such as AlliedSignal Inc., which has come up with proprietary materials that are applied to wafers with a spin-on tool. Those materials are much more expensive, but the deposition tool is less complicated and less expensive than a CVD system. Both technologies seem to have problems, although the companies involved in the efforts say they are very close to being ready.
"We feel the materials are ready for volume deployment," said David Richter, marketing director for AlliedSignal Electronic Materials (Sunnyvale, Calif.), the company's division for semiconductor materials. AlliedSignal has two materials that deliver k values below 3, and has successfully implemented them into sample chips with seven layers of metal at its own wafer fab, although no chip companies are using it for any volume designs. "It's just a matter of integrating the material into production lines," Richter said.
AlliedSignal has also recently opened a $30 million facility in Silicon Valley to study low-k material and deposition techniques, in order to help its customers push the technology into their volume-production lines. Richter noted that implementing the copper-interconnect technology was a big thrust last year in the chip industry, and that semiconductor companies are now starting to move on to dielectric materials. "The chip companies are only willing to choke down one big change at a time," he said. "We believe that the time for low-k is coming very quickly."
Ron Dornseif, principal analyst for semiconductor materials and manufacturing at Dataquest Inc. (San Jose, Calif.), said using a spin-on tool is a big change for chip companies that are used to using CVD systems. "The low-risk way to go is to use what you are familiar with, and for most companies that means CVD," he said.
Applied Materials has a low-k material, Black Diamond, which uses existing CVD tools, and rival Novellus announced its own CVD low-k entry, Coral, last month. Applied also rolled out one more piece of the puzzle at Semicon — a low-k barrier film that can be used for etch stops and as the barrier between the dielectric fill and the copper. "Nobody else has focused on the dielectric barrier yet, but it is a critical part of reducing overall capacitance," said Ian Latchford, global product manager for Applied's plasma-enhanced CVD materials in Santa Clara, Calif. "We are at least six months ahead of our competition."
However, analyst Hutcheson said neither camp has worked all the bugs out of the technology. While the spin-on low-k materials do offer k values below 3, they often tend to be too soft to work with copper because the harder metal will nick the surface of the dielectric layers. "You can do a really good low-k layer with spin-on tools, but you just can't make it work. There are too many problems right now to integrate it with copper in production," he said. The CVD tools also have drawbacks, mostly related to the complicated process recipes required to create and deposit the material.
"Low-k is a big mess right now," said Hutcheson. Although he expects to see it become a standard part of the semiconductor manufacturing process, it's hard to say exactly when. "All the issues related to 300-mm wafers have gone from a big question to an answer, and copper isn't a question, but it isn't quite an answer yet, either. But low-k is still a question." |
