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To: Elmer who wrote (86132)7/26/1999 12:48:00 AM
From: kapkan4u  Respond to of 186894
 
<but in regards to FPU, some of the Coppermine improvement was the result of "complier technology". Now I don't know exactly what was meant by that but it could involve the use of SSE instructions for FPU code.

I would argue that performance improvements due to Intel compiler's specFP tweaks are nothing more than a marketing gimmick.

Kap.



To: Elmer who wrote (86132)7/26/1999 1:05:00 AM
From: Scumbria  Respond to of 186894
 
Elmer,

Incidentally, if Intel produces the long rumored "Cascades" followon to Xeon, that being a Coppermine with anywhere from 512K to 2 Meg of L2, it would make sense that the performance would exceed the K7 in it's existing form.

Dream on....

Scumbria



To: Elmer who wrote (86132)7/26/1999 10:52:00 AM
From: Ali Chen  Read Replies (1) | Respond to of 186894
 
Elmer, <Fullspeed offchip L2 is equally unlikely due to manufacturing problems and testability with an ultra-highfrequency BSB,
untestable with today's manufacturing technology.
AMD's only hope seems to be...>
So, you are saying that we will never see a Xeon above
550MHz since Intel still lives on the same planet and
therefore also have no equipment to effectively test the
"ultra-highfrequency" SRAMs. Is it what you are saying?