Hello Everyone,
Per my last post - the Rambus article we released in the June Issue of our Monthly Letter. We readily acknowledge that there has been other news so some of these comments will be updated in the next article we release on this subject.
Technology Report: Rambus Manufacturing
by Ron Leckie
Seldom before has one innovation created so much excitement, hype and
opportunity in such a short period of time as has been created by Rambus, Inc. (RMBS). In this article, we will review the Rambus technology and the semiconductor manufacturing impact.
What Is Rambus?
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Essentially, the Rambus intellectual property (IP) is a set of designs and design rules that enable high-speed memory data transfer between a processor and its DRAM memory. The memory controller in the processor contains a Rambus Interface (logic circuit) that contains the intelligence to re-format the processor's instructions to and data from the external memory. It has to alter the voltage levels, timing and grouping of the signals to enable them to be blasted at high speed through the Rambus Channel to / from the
memory. At the other end, on the memory chip(s), there is similar interface logic to re-format the signals to address the DRAM core memory. This is an open architecture, but must be licensed from Rambus to be used.
The Rambus Channel incorporates a systems level specification, which defines the signal timing, pin-out, layout, etc for the high-speed signals. These techniques are not new to mainframe computer or test system designers who for many years have used such transmission-line design rules to lay out printed circuit board designs for ECL (emitter coupled logic). However, their applicability to CMOS logic is new and offers some of the Rambus "magic".
The Rambus architecture supports 16 (or 18) high-speed data channels, 8 high-speed address channels, and 4 high-speed clocks. In addition to those 30 high-speed channels, there are 32 power and ground pins for a total pincount of 72 on the direct Rambus DRAMs (D-RDRAMs). Essentially, the Rambus Channel delivers in each 10 ns (nanosecond or 1/1,000,000,000 second), eight sets of encoded address information on the 8 address channels, and eight sets of data on the 16 (or 18) data channels. This delivers two bytes (each 8 bits) of data, eight times every 10 ns across 16 channels. Rambus describes this as 800 MHz data rates per pin, but since it is limited to 16 channels and grouped for a given address in 10 ns increments, we prefer to think of it as 128 bits of data delivered every 10 ns, or equivalent to a 100MHz rate.
Just to clarify any confusion about the 16 vs. 18 data number, some memory designs use an extra bit for every 8 bit word to track parity. This enables system designers to be able to detect any dropped error bits and correct for them at the system level. As memory designs run faster and silicon geometries drop below 0.18 micron, we expect to see more use of parity to compensate for increased data fragility. So, look for more 72, 144 and 288
Mbit memories in future. Obviously, these slightly larger memories will cost more.
What Will Rambus Do For My System?
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We have been trying to find out more about the system level performance side of the Rambus equation, but with little success. The company has been particularly poor at returning answers to our questions. In talking around the industry, it is the common belief that on today's PCs we will see little improvement.
Consider what we said before about each address delivering 128 bits of data at 100MHz rates. This same data rate could be achieved with PC-100 SDRAMs by taking eight, 16 bit wide by 4Mbit deep devices, for a 512 Mbit or 64 Mbyte memory. However, today's processors only have 64 bit architectures, so they cannot take full advantage of the 128 bits delivered by Rambus each 10 ns cycle.
The reason that Rambus has been so popular to date with the game
manufacturers like Nintendo and Sony is that they do not need huge 64 Mbyte system memories. They need to have 16-bit data streamed very fast from a single chip. Rambus was an ideal solution for the Nintendo 64, which is now hitting end-of-life, and the new Sony Playstation II product which is just coming on to the market.
In terms of PC performance, even Rambus CEO, Geoff Tate, said at a recent conference that, "Rambus offers much better performance headroom", but the implication is that it does not yield much improvement today.
Much of the system-level performance will be determined by the architecture, the use of cache memory, and the latency (time taken to switch from write to read mode). There is a lot of skepticism about Rambus' PC system performance, because there is no engineering data available. All working systems are prototype "kludges" in the labs, and nobody seems to want to share the data. Intel's Camino chipset will be the first to take advantage of Rambus, but it is now delayed until late September for production start. Clearly, Intel is convinced about what Rambus will do for their processors. In recent generations, processor performance has been limited by memory
bandwidth. Rambus promises Intel more processor performance headroom and will add value to the processor. Another example is that we believe that the latency on Rambus is a good match for the latency on the Pentium III. These are complex issues, which we cannot resolve, but in due course we will see the data - and it will not lie.
What Are The Manufacturing / Cost Issues?
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None of the Rambus features come for free. There are significant cost implications in terms of die size, packaging, yield, testing, the system and of course royalties. The questions are "how much is the cost premium?" and "will I get sufficient performance for that premium?"
Thomas Pabst, of Tom's Hardware Guide, gives an analysis of RDRAM vs. SDRAM costs at his website:
www5.tomshardware.com
He states that with the Camino chipset, "the new RDRAM can't really show earth-shattering improvements", and there is a significant penalty to pay to get it. The data, which he got from a major memory supplier, shows that "RDRAM goes for about six times the price of PC133, or ten times the price of PC100."
infras.com
While we can't quite substantiate such an alarming price disadvantage, we will look at each of the various cost issues that contribute to this in some detail below.
Cost #1 - The die size penalty
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On the logic processor, there are two Rambus functions to be added. The Rambus ASIC Cell (RAC) is the circuitry that interfaces through the external pins to the Rambus Channel. It comprises two delay locked loops, input-output driver cells, shift registers and multiplexers. The Rambus Memory Controller (RMC) provides the protocol control and synchronizes between the processor and the RAC. We do not know how much silicon real estate is taken up by the RAC, but the RMC occupies between 10,000 and 14,000 gates. On a 10 million-gate processor, the Rambus overhead is relatively minor, especially considering the price of the chip.
On the RDRAM chip, we see a very different story. DRAMs are commodities and in manufacturing, every cent is counted. We have heard from both Micron and Samsung that on the 128 Mbit RDRAM, the logic interface overhead is in the range of 20 percent to 25 percent in addition to the base DRAM array. Any increase in die size has a double "whammy" fewer gross die per wafer, and lower attainable yield due to defect probability. Hyundai, for some reason quoted 10 percent or less for their comparable overhead number, but we find that difficult to comprehend unless they are using many more metal interconnect layers which would add a process cost burden as well.
The 20 to 25 percent numbers are more consistent across vendors, and are quite alarming. The big concern is about how this logic interface overhead will scale down as feature sizes are reduced and memory cell count grows in subsequent generations. The 64Mbit RDRAM is stillborn, other than for the games market. The 128/144 Mbit RDRAM will be there for the early adopters, but the market sweet spot will not arrive until the 256/288 Mbit generation. The question is how much overhead will that have at 0.18 micron? In a recent panel discussion, the consensus from Geoff Tate and several RDRAM supplier executives was that it should end up in the range of 7 to 10
percent in the long term.
Cost #2 - The Packaging Penalty
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The ideal package for RDRAM chips is the micro-BGA (Ball Grid Array), chip scale package. Its small size and short lead lengths give the performance necessary. Prior DRAM generations have been predominantly shipped in TSOP packages costing around $0.007 per pin. The micro-BGA packages today cost $0.02 per pin, and at 72 pins, this is a significant cost adder. However, this package is still in its infancy and, as volumes ramp up, that cost will come down. We have heard experts at Amkor (AMKR) confidently project that it will come down below the TSOP to $0.004 per pin over the next 1 to 2 years.
As a result, we feel that while initial packaging costs will be higher, this will soon become a non-issue.
Cost #3 - The Yield Penalty
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We heard Farhad Tabrizi, Strategic Marketing Director at Hyundai, recently state that a 64Mbit SDRAM today, selling for $7, would have to sell for $11 in the Rambus version to account for the die size penalty, assuming no yield impact. However, because of their current low yields, that same part would need to sell for $24 today. Clearly this will not work.
The yields at Hyundai seem to be down around 30 percent. This may be one of the lowest, but from what we hear, everyone is suffering from low yields today. Most of the fall-out is due to high-speed failure modes. Unlike logic suppliers, DRAM manufacturers have historically not had to deal with high-speed timing since DRAMs have always run at speeds below 100 MHz. As one person said, "There was so much margin that you could drive a truck through the timing specs!" Not so with Rambus. The designs, processes and test methods will need to be fine-tuned to optimize the circuitry to make it manufacturable at the 800 MHz that the market wants.
Admittedly, today there is no production volume to speak of, but what there is can meet the 600 MHz for Sony Playstation II. However, there is significant fall-out at 700 MHz and much less yield at 800 MHz at most vendors. There are rumors on the street that Micron (MU) may have had a breakthrough in yield improvement, but we have been unable to confirm this. These yield problems will be solved the questions are when, and how much?
Cost #4 - The Testing Penalty
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A lot has been written and surmised about the test strategy and costs
involved when testing RDRAMs. In truth, the jury is still out. The big wild card is the yield issue described above.
Many have estimated the test capital re-tooling costs for RDRAMs at $15 to $20 million for each capacity increment of 1 million units per month. This is close to our back-of-the-envelope calculation for what it would take today, but it should drop to half of that in 1 to 2 years. However, it could be either much higher or lower, depending on the test strategy employed at the memory chipmakers.
If there were no significant yield fall-out at high-speed, then most
manufacturers would opt to buy the new 800 MHz test equipment only for exercising the interface logic with Rambus' MOAV (mother of all vectors <grin> - a 1 million vector set standardized by Rambus), and a simple memory pattern. This complete test set, at various voltages, for a 128 Mbit part should take no more than 20 seconds on a Rambus production tester costing around $5 million. Prior to this, in a separate insertion, they would perform exhaustive pattern tests on sub-100 MHz testers by addressing the RDRAM in Direct Access mode, bypassing the Rambus interface. Of course, these sub-100 MHz testers could even be "free" as most DRAM manufacturers have excess capacity on bought-and-paid-for older generation systems. The test times would be longer, in the range of 5 minutes or so at each of room temperature and high temperature, but the overall test cost would be lower.
To reduce test costs even further, most DRAM manufacturers are actively working to migrate the slow-speed exhaustive pattern tests forward to the wafer probe stage. Here, they can be performed cheaper, and have the advantage that many defects may be repaired in the subsequent laser repair process. Historically, only about 30 percent of all testing was performed at wafer probe. The barrier was getting the high-frequency probe tooling in place to operate at 70+MHz on multiple devices in parallel. Solutions are now available for this, and several suppliers are targeting at increasing probe to cover 80 percent of all memory tests within the next year. This
leaves only 20 percent to be handled by expensive full-performance test systems.
Of course, this assumes minimal high-speed yield loss, and that does not look possible for some time.
What we think will happen, is that when Camino is released later this year, and the production ramp approaches, tester decisions will be made and initial production orders placed. Manufacturers will initially have to over-order to satisfy full at-speed test demand, but as yields improve, they will migrate as much of the test load as they can to probe. This will provide incremental virtual capacity at final package test, and slow down demand for these expensive, high-end test systems. The DRAM business is nearly always caught in the squeeze between market pricing and aggressive cost reduction. This results in an aversion at most manufacturers to spending huge amounts of money on expensive test capital. All of the delays to the Rambus ramp have given more time to the chipmakers to work on yields,
test strategy and tester selection. As a result, there are still many decisions to be finally made.
Cost #5 - The System Penalties
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There are burdens, too at the system level. For example, RDRAM has a higher power dissipation at around 1.8 Watts. However, the architecture employs power management techniques to put the chips in a sleep mode while not being used. With, say, 8 or 16 chips on the RIMM memory module, only one chip is addressed and is heating up any one time. This is good to manage the total heat down, but the source of the heat moves around the board. Hence, it is necessary to add a clamshell heat spreader to both sides of the RIMM module. This can add tens of cents per module to the cost.
The high-frequency signals must travel along controlled impedance traces on the printed circuit boards, both on the RIMM and the motherboard. These boards now need to be made to tighter specs of +/- 10 percent tolerance which is tighter than they have historically had to deal with in the PC industry. This will add a small cost premium.
Cost #6 - The Royalty Burden
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According to Rambus, the royalty fees in its licenses range from 1 percent to 2 1/2 percent, depending on the nature of the agreement. The consensus is that it averages at about 1 1/2 to 2 percent for most DRAMs. This does not seem like a huge number, but as we said before, every cent counts. Also, the industry has a very large emotional dislike for royalty fees.
How Quickly Will Rambus Be Adopted?
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Intel's Camino chipset will supposedly be ready to support Rambus DRAM-based PC introductions before the end of the third quarter. Apparently, Advanced Micro Devices (AMD) is expected to announce later this summer that its new Athlon K7-based chipset will support Rambus DRAMs. Intel has also "qualified" memory chips made by Hyundai and Infineon that use Rambus technology, and Micron has said that development of Rambus memory chips is its most important initiative. There are yield and cost issues to be resolved, but the designs are coming. However, so far, Dell is the only PC maker to step-up and commit, with most other PC suppliers refusing to pay
the Rambus premium. (As a side note, we have heard that Dell's CEO and CFO have each made significant personal investments in Rambus, so they may have some motivation to forge ahead).
As we said earlier, the 64M RDRAM is too late for the PC market, and several 128/144M parts have been qualified by Intel, but with 4 suppliers shipping 256M SDRAMs this year, the market will soon need the 256/288M generation of RDRAM.
We spoke recently with Sherry Garber, Senior Vice President at Semico
Research Corp., Scottsdale, Arizona. Her view is that the Rambus DRAM volume will be tied primarily to high-end system and server sales. She believes that the cost premium will prevent it from penetrating the sub-$1,200 PC market and the increased thermal dissipation will keep it out of the laptop market, which is the fastest growing PC segment at 25 to 30 percent annually. As a result, she currently expects to see only 9 percent of the DRAM market comprising the Rambus architecture by 2003. This is
significantly short of the 40 to 50 percent being touted by Rambus and the chip manufacturers, but we sense that her healthy skepticism may be closer to reality.
infras.com
The Tester Selections
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There has been much debate about the Rambus tester choices that are faced by the memory manufacturers. The memory test incumbents are Advantest and Teradyne (TER), and then Hewlett Packard (HWP) and Schlumberger (SLB) have seen Rambus as an opportunity to enter this sector. Even Japanese player, Ando Electric, who has lost significant memory test market share, has just entered with a Rambus tester.
Hewlett Packard is the Rambus incumbent at many suppliers due to the fact that they had the only (logic) tester at the time that could test in the 600-800 MHz range, so it was used for prototype characterization. This has been evolved into a memory tester with some software-derived pattern generation capability, etc. We believe that initial benchmark results indicate that this system has a significant overhead, resulting in some of the slowest test times. This will be a significant issue in production.
Schlumberger entered the DRAM memory test market a couple of years ago by developing "Dragonfly" in partnership with Samsung. The system arrived just as the bottom fell out of the market and only a handful has been shipped. Thus, their memory test experience is limited. Their Rambus tester is based on their logic system architecture and is reputed to have the best overall timing accuracy.
Neither HP nor Schlumberger have track records as memory tester suppliers, and the customer base puts a heavy emphasis on re-using their experienced incumbents. Additionally, these two suppliers have chosen to ignore the wafer probe market by bringing systems to market without error-capture and redundancy analysis capability. If chipmakers do indeed drive test more to wafer probe to cut costs, then these two players will suffer.
Teradyne's Aries tester is based on their logic system architecture, but also utilizes their strong algorithmic pattern generation (APG) and error catch / redundancy capabilities from their memory systems. The system accuracy is very close to that of the Schlumberger system and its test times are ahead of the pack.
Advantest's T5591 system came out with significant clock jitter problems, which precluded them from meeting the timing accuracy specifications. They report that this has been resolved, but we know from experience that these kind of problems are non-trivial. They are bringing out their new "RM2" system by year-end to cut the cost of Rambus test by 75 percent. The plan is to do this by scaling it to expand the number of parallel sites from x16 to x64, and keep the total system cost, including handler to around $6.5 million. The problem we see with a x64 approach is that firstly, it will only make the accuracy spec more difficult to attain, and secondly, if bulk
memory tests are off-loaded to cheaper testers at probe, then the high-speed test times will not be efficient at high levels of parallelism.
While the HP and Schlumberger systems are targeted almost exclusively at Rambus, the Teradyne and Advantest systems are more flexible architectures for testing any high-speed memory at either package or probe test. With the skepticism about Rambus' market penetration vs. SDRAM, we see this as a key consideration for memory manufacturers. This, plus their extensive memory test experience, is what we believe will keep them in the top two positions.
We expect to find out more at Semicon West, and will update subscribers next month.
Investment Thesis
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In terms of Rambus as an investment opportunity, we should look at revenue potential. DRAM sales are forecasted to come in around $14 billion this year and grow to the $30 billion to $40 billion level by 2003. If we take the $30 billion forecast, Sherry Garber's 9 percent penetration, and a 1 1/2 percent royalty model, this would only bring in $40 million in royalty fees to Rambus in 2003. At the high end of each range, the number increases to $300 million still not a lot to support today's $2.2 billion market cap for RMBS.
The company has stated that headcount is currently at 160, but would only be growing at 5-7 per quarter next year. This would lead us to expect expenses to be well contained. However, our futile experience in trying to reach experts at the company would indicate that they are grossly under-staffed and will have to add staff at rates higher than suggested to satisfy the customers and industry communities.
Rambus will continue to get revenues from licenses, contract revenues and logic royalty fees. Current revenues are around $40 million annually, with 75 percent of that being license fees and contract revenues. Future growth is expected to come mainly from the royalty streams. Logic royalties will be based on much lower unit volumes, but higher ASPs. Intel, their biggest logic licensee has "driven the hardest bargain" per CFO, Gary Harmon, in terms of royalty percentage. So, if we assume that logic are equal to memory royalties, then this would put revenues in 2003 somewhere between
$120 million pessimistically, and $640 million optimistically. This is a wide range, but with the risks involved, it is hard to predict 4 years out. We believe that Rambus is currently valued based on the optimistic level discounted out 4 years this is why we will not be buying the shares for our portfolios.
For a capital equipment supplier investment, the main opportunity comes from the tester manufacturers. We would not invest in either Schlumberger or Hewlett Packard purely because of their tester businesses far less their Rambus potential. These conglomerates are more heavily influenced by their primary, non-semiconductor businesses. Teradyne, as we have said all along, is the leader from an ATE investment perspective. We think they will do very well with their Rambus strategy, and could quite well gain market share
from Advantest. However, it will not be a huge impact to their overall business, which is certainly strong in semiconductor ATE (especially mixed signal and system-on-a-chip), but is diversifying well into other businesses. Advantest is the closest to a pure play in the memory test arena. If you can trade on the Tokyo exchange, then this is worth looking into, as they will certainly participate in the high-speed memory test market. It has only doubled off its 12-month low, whereas Teradyne has come up more than 4 1/2 times from its 12-month low.
Despite the clear excitement about the Rambus technology, we cannot bring ourselves to jump onto this particular investment "bandwagon". Yes, memories are getting faster at last, and it will bring a lot of challenges and opportunities for the industry, but remember a memory is a memory, but above all else, it is the most aggressive commodity in the semiconductor marketplace. Manufacturers will continue to struggle with the age-old cost vs. price pressure challenge. Remember what we have said before - the 1993-1995 time period, when memory manufacturers made money hand-over-fist, was an aberration!
Hope you all enjoyed the article.
One more time: Your feedback is welcome.
Regards,
Carl
INFRASTRUCTURE
infras@infras.com
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