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To: Scumbria who wrote (86270)	7/28/1999 2:22:00 PM
From: Ali Chen	Respond to of 186894

Scumbria, <You and Ten are both correct.> No, one of us is much more correct than other. Ten is claiming that higher SlotA bandwidth is of no use, and that the memory bandwidth must match the CPU bus. This could be true in old Socket-5 Intel days when the simplicity of synchronous clocking along busses was the state of the design art. With clock-forwarding and sophisticated FIFOing this is no longer the problem (except for Intel designers who still could not master this according to the recent snooping "errata" in all Pentium-II, III etc.) <A certain percentage of the time a computer spends doing a task is processing time, and a certain percentage is time spent waiting for memory/IO.>... ..and a certain percentage of this time is overlapped, and a certain percentage is going to restart pipelines after dependency resolution, and...., and.... :) :) Therefore, a blatant proclaiming the memory as one and only one bottleneck is a bit of a stretch. After all, faster CPU channel reduces its own latency at least, and snoop response time. Therefore, hurray to Athlon 200MHz bus that will kick Pentiums butt. How about that?