SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: grok who wrote (67089)7/30/1999 5:37:00 PM
From: fyo  Respond to of 1576926
 
KZNerd - Re: At 6 transistors per cell 32KB of cache has 6*8*32K=1.57M transistors in the array. Of course there are tags, cam, decode, etc but it'll never get you to 3M.

I wouldn't know.
It wasn't my quote, but rather Tench's.

That said... looking at the numbers given at sandpile.org, the number seems very close to 2M per 32KB (more for smaller caches, less for larger).

--fyodor



To: grok who wrote (67089)7/30/1999 8:28:00 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 1576926
 
<At 6 transistors per cell 32KB of cache has 6*8*32K=1.57M transistors in the array. Of course there are tags, cam, decode, etc but it'll never get you to 3M.>

It's purely an academic argument. I guess the real figure stands somewhere between 1.5M and 3M transistors per 32K, depending on cache tags, supporting logic, etc.

Tenchusatsu


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News