Powerful New Processor Eliminates Need for Hardware Design
Design Focus Becomes Software-Based, Cutting Development Time and System Cost in Half
Texas Instruments has launched a new era in product development by
simultaneously unveiling an unprecedented 1600 MIPS microprocessor
high-level programming language (HLL) support that achieves virtually
the same performance as hand-tuned assembly language. The computing
power of the new TMS320C6x ('C6x) generation digital signal processors
(DSPs) promises to change the way new products are designed. They easily provide the demanding performance needed to enable communications applications and emerging real-time applications such as automotive collision avoidance and intelligent home management. The benefits to OEMs include smaller product-development teams, faster time-to-market, and programmable flexibility, all at performance levels that have previously been attainable only with complex custom hardware solutions. Software Moves to Center Stage for Fast Time-to-Market
To take advantage of processor architecture, DSP application developers have historically maximized software performance through an often time-consuming process of hand-optimizing code. The efficiency of the 'C6x software tools allows software engineers to program in high-level C code, without concern for the mechanics of the underlying processor platform.
The benefits of shifting the paradigm from hardware to software includes cutting development time in half for DSP-based products, and access to a widely expanded talent pool of application software developers. These developers, who may be DSP neophytes, can immediately take advantage of the power of the 'C6x, the world's highest performance generation of DSPs. With the 'C6x, developers can program in highly-structured and architecture-independent C code, dramatically reducing development time while still achieving unprecedented performance.
Mainstream application programmers who don't intimately understand
underlying hardware constructs can now tap the full power of a
high-performance DSP processor. The 'C6x development tools provide DSP
programmer productivity with the easier expression of mathematical
algorithms without the need to specifically map an algorithm's execution onto the processor architecture. HLL programming lets programmers focus on their application-level core competencies by effectively hiding the architectural details of a DSP. This decreases the time it takes to develop a DSP-based product by making DSPs easier to program, and DSP application software easier to reuse.
Fine Tuning With DSP Industry's First Assembly Optimizer
Some key applications kernels can still benefit from the performance
tuning that is achievable with assembly language coding. Because of
this, TI has developed an Assembly Optimizer for the 'C6x generation
processors. Assembly language programmers can now have the kind of tools that were previously only found in HLL programming. The 'C6x Assembly Optimizer lets programmers transparently target the 'C6x's advanced Very Long Instruction Word (VLIW) architecture by automatically scheduling and automatically parallelizing instructions from serial, in-line assembly code. The 'C6x Assembly Optimizer shields programmers from having to understand the minutiae of the underlying processor architecture by allocating processor resources such as registers and memory address locations. This level of tool elegance is unique and unprecedented at the assembly level.
Programmable Flexibility With the Performance of an ASIC
To accommodate the performance needs of applications such as
multi-channel communications infrastructure equipment, system developers have classically had to turn to custom hardware designs to handle huge amounts of data throughput. While application-specific integrated circuits (ASICs) have historically enabled designers to achieve performance well beyond the capabilities of programmable processors, ASIC development is time-consuming, risky, and inflexible relative to software programming.
The new design standard enabled by TI's 'C6x DSP processor generation
gives product developers the same performance level of custom ASICs, but with the flexibility of a programmable processor. The 'C6x eliminates the need for time-consuming and expensive custom hardware design, allowing designers to instead focus, for the first time, on developing their products in software. Furthermore, while even a minor design alteration can take months with an ASIC, changes such as those required to accommodate shifting standards in communications protocols can take only minutes with the 'C6x, but without compromising system performance.
Tiny Core Yields High-Performance at Low Cost
Modern superscalar RISC and CISC microprocessors typically use a great
deal of on-chip hardware to optimize the scheduling of computing tasks
for the CPU while software is running. The 'C6x generation's
ultra-efficient C compiler handles instruction scheduling in software
before the code ever gets run on the chip. Consequently, 'C6x generation DSPs achieve a tremendous level of performance but use very few transistors relative to other processors. The result of such spartan useof silicon is far lower price/performance, and improved device yield and reliability.
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---Industry's Fastest and Most Integrated DSP from Texas Instruments Powers Third-Generation Wireless Base Stations and Telecommunications Infrastructure
TMS320C6203 DSP Today Designed into Eight out of Top 10 3G Wireless Base Station Original Equipment Manufacturers
HOUSTON, (May 24, 1999) - The world leader in digital signal processors (DSPs) and analog, Texas Instruments (TI), today introduced the industry's fastest DSP that runs at 300 megahertz (MHz). The new device integrates 7 megabits (Mbits) of memory, the largest amount of memory on any single-core DSP to date. The combination of speed, performance and integration will drive multi-channel, multi-function applications like third-generation (3G) wireless base stations, telecommunications and network infrastructure equipment. See www.ti.com/sc/c6000
Executing 2400 million instructions per second (MIPS), the TMS320C6203
reduces the overall system cost by packing more channels into less space with lower per-channel power consumption. Among the companies which have made the decision to use the 'C6203 in their 3G wireless base stations is Ericsson, the world's largest supplier of wireless systems. In making its choice, Ericsson cited the high level of system integration and performance offered by the 'C6203.
"Designers can begin developing today because the new 'C6203 is code-
and pin- compatible with the currently sampling 'C6202 at 250MHz," said Pradeep Bardia, product marketing manager, Texas Instruments. "The 'C6203 is the sixth code-compatible member of the world's
highest-performing DSP platform which clearly shows that TI is not just making promises for DSP performance: TI is delivering many products on the industry-leading performance architecture."
TI's Innovative New Process Enables Increased Speed and Integration
The 'C6203 breaks ground with a new 0.15-micron L-effective (0.18-micron drawn) Complementary MOS (CMOS) manufacturing process, both increasing transistor speed and lowering power consumption to allow a higher level of integration in minimal space. The device operates with a 1.5-V internal voltage and 3.3-V I/O voltage; therefore it only consumes 330 mW of CPU power while executing 2400 MIPS at 300 MHz.
With 3 Mbits of on-chip program static random-access memory (SRAM) and 4 Mbits of on-chip data SRAM, the 'C6203 enables system designers to
eliminate the need for any external memory for high performance,
multi-channel applications. Software does not incur the delays inherent in using off-chip memory, and hardware does not require the additional board space and expense in cost and power of external memory devices. Integrated peripherals include dual 32-bit buses (an external memory interface (EMIF) bus and an expansion bus); three multi-channel buffered serial ports and two 32-bit timers. The 0.15-micron process technology allows the 'C6203 to be fabricated in an 18-mm2 (0.4 square inch) ball-grid array (BGA) package resulting in even greater space savings in high-density systems.
Performance Enriches Multi-Channel Applications, Accommodates Full T-1
Span
With its high performance and large on-chip memory, the 'C6203 will
allow original equipment manufacturers (OEMs) of telecommunications
equipment to pack more channels into less space, thus enabling a variety of applications like V.90 modems.
"A full T-1 span of V.90 modems on a single chip is now reality," said
Amnon Gavish, Ph.D., and CEO of Surf Communication Solution Ltd. "As a
result of using the 'C6203 with 7 Mbits of internal memory, we will
achieve the highest modem access density and widely outperform other
solutions implemented on dedicated modem chips. The 'C6203 combined with Surf's open-system design delivers complete universal access convergence of data-modem, voice and fax along with advanced management, diagnostic and quality of systems benefits. Our time-to-market will be slashed because our existing 'C6000 solutions will be migrated with little effort to the software compatible 'C6203."
Additional key applications that the 'C6203 addresses are 3G wireless
base stations, which will enable the delivery of data, video and other
types of information along with voice over wireless telephone links. The 'C6203 DSP today is designed into eight out of the top 10 3G wireless base station manufacturers.
Converged wireline networks, which deliver voice, video and data on the same line, will also require the processing power of the 'C6203. Telecom switches, programmable xDSL modems, imaging systems, videophones and videoconferencing systems, multi-channel vocoders and voice gateways will also benefit from the greater performance and integration of the 'C6203.
New TI Analog Components to Support 'C6000 Platform DSPs for Faster
Time-to-Market
As the world leader in analog for a second consecutive year, TI
continues its commitment to provide data converter and power management products for TMS320 DSPs with the new 'C6203. TI now offers a pin-compatible 8-12 bit family of high-speed digital-to-analog
converters (DACs) that are tailored to communications applications and
ease communications system design. These three new 8-12 bit, 100
mega-samples-per-second communications digital-to-analog converters
(CommsDACs), which are designated as the THS5641, THS5651 and THS5661
respectively, are able to improve the efficiency of a system's DSP.
"By releasing this CommsDAC family with the 'C6203 DSP, TI provides
communication systems designers with a complete solution of digital
signal processing and analog interfacing products, which help optimize
system design and shorten time-to-market," said Tom Lahutsky, new
product development manager for TI's Mixed Signal Products Group.
TI plans to support a complete base transceiver station solution
reference design, which includes four analog-to-digital converters and a 4-channel digital down converter. In addition to the CommsDACs, TI also offers leading-edge power management solutions for the 'C6203 in the forms of the TPS5615 processor power supply controller (supports 1.5 V core) and the TPS7133 (supports 3.3 V I/O). For more information, see
ti.com and
ti.com.
The 'C6202 device, which is sampling today, is code- and pin-compatible, allowing designers to get a head start with 'C6203-based system designs. The 'C6203 and the 'C6000 platform feature the industry's most sophisticated suite of development tools, including the best-in-class C compiler, that deliver unprecedented time-to-market advantages and the largest network of third parties in the DSP industry.
Programmers can download Code Composer™, TI's leading-edge development
environment for the 'C6000 DSP platform, for a free 30-day evaluation.
Future plans include a rich spectrum of industry-standard vocoders and
algorithms from third parties to help further reduce time-to-market. |
