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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (67244)	8/1/1999 4:50:00 PM
From: Ali Chen	Read Replies (1) \| Respond to of 1573943

Dan3 <One last comment on rambus - then I promise I'll stop> No, no, please continue. I only want to comment on unfair terminology. When you are referring to RAMBUS, you are saying "800MHz", while when talking about DDR SDRAM, the numbers usually are much lower - 200 and 266. For an unsophisticated investor (I don't want to point fingers here, we all know them:), the 800 sure sounds better than 200. However, the theoretical Rambus bandwidth is 800x2=1.6 GBytes/s while one SDRAM DIMM has 200x8bytes = also 1.6GBytes/s, and 266x8=2.1GB/s. And we do not talk yet about typical 4-way interleaving in servers as you commented in your post. Therefore, I would encourage you to find a way to always stress this simple advantage when discussing RAMBUS vs.SDRAM, just to remind them :) On another note, the current cheap PC-100 SDRAM has a bandwidth of 800MB/s. However, if you try to measure an actual memory bandwidth in a Pentium-XXX system (using, for example, famous STREAM benchmark by Dr. J.McCalpin reality.sgi.com ), the typical Pentium-II bandwidth will not exceed 350MB/s, or about half of the theoretically available memory bandwidth: cs.virginia.edu Why? Because apparently the Intel CPU/bus cannot provide an adequate data flow due to internal design limitations. Remeber someone was talking about severe memory bottlenecks on these SI threads? Regards, - Ali

To: Dan3 who wrote (67244)	8/1/1999 7:23:00 PM
From: grok	Read Replies (2) \| Respond to of 1573943

RE: <A server using 4 way interleaved DDRSDRAM 266 will have a significant advantage over one using DRDRAM...> People designing in drdram in a large server would use many multiple rambus channels. For example, the 21364 Alpha chip supports 4 rambus channels on each processor and, I think, they plan on at least 64 processors so you'd have 256 channels and massive bandwidth and latency will be low since the channels attach right to the processors with no chip set in the way. I don't know if this architecture will dominate since it is a Non-Uniform Memory Access (NUMA) architecture and has sw issues. But other architecures are also easily supported with multiple channels due to the low pin count of the drdram channel. The biggest problems that rambus has in highend servers comes from RAS (Reliability and Serviceability) issues. For example I don't see how you can do pair matching with drdram since you can't mess with loads. Also, I heard it said that with drdram ecc you can't implement the "chip kill" feature of operating even if an entire dram dies. I don't know if either of these issues are fundamentally unsolveable problems for rambus but I know that certain server designers are ruling it out for today's designs.