To: Dan3 who wrote (67446 ) 8/3/1999 12:37:00 AM From: Tenchusatsu Read Replies (2) | Respond to of 1574356
Dan, and perhaps KZNerd as well, Every SDRAM module (a.k.a. DIMM, or Dual Inline Memory Module) consists of at least eight chips. Each chip is manufactured at some density, like 64 Mbit, 128 Mbit, etc. So a typical 64 MB (that's MegaByte) SDRAM module consists of eight 64 Mbit chips. The problem is that for SDRAM, you can't go below eight chips without hurting bandwidth. All eight chips have to work together in unison to provide 0.8 GB/sec of bandwidth (PC100). That's where DRDRAM comes in. A single DRDRAM chip is capable of supporting the full 1.6 GB/sec of bandwidth. In other words, if current memory densities were high enough, you could put all 64 MB of memory onto one DRDRAM chip and your performance will not suffer. Adding more chips to the same channel will only increase total memory capacity. The bandwidth still says at 1.6 GB/sec. Therefore, as memory densities increase faster than the value market segment demands, DRDRAM allows system builders to go with fewer and fewer memory chips. This helps to save on costs over SDRAM which always requires a minimum of eight chips. That's one reason why Timna will be supporting an integrated DRDRAM controller. By the time Timna hits the market, memory densities will have increased to the point where representing 64 MB of memory using, say, two 256 Mbit DRDRAM chips may be cheaper than using eight 64 Mbit SDRAM chips. (This is assuming, of course, that production of 256 Mbit DRDRAM chips ramps up in time. If not, well, four 128 Mbit DRDRAM chips will have to do in the meantime.) By the way, the same cost arguments apply to PC133 SDRAM and DDR SDRAM. Tenchusatsu