To: Dan3 who wrote (26650 ) 8/9/1999 2:21:00 AM From: J_W Respond to of 93625
Dan, Wow, I spend the entire day at the hydroplane races (Seattle Seafair) and I get back to find 40 new posts, many referencing new information I hadn't seen before. Talk about information overload. <gg> I appreciate the fact that you took the time to fully read Dell's white paper on Rambus. Not everyone that should actually does this. Makes for a much better discussion for everyone. I consider these and other white papers to be very important as the companies writing them have much at stake. Their future success or failure is on the line. Contrast this with web sites that publish test results, where they risk relatively little in comparison and you can see why I take this position.If you look at the paper carefully, you'll see the implication that a substantially faster memory bandwidth, especially one that can stream data at those faster rates instead of bursting it, yields a performance increase. Between the lines, it seems to say that this will more than make up for a slightly higher latency. I would have to agree with your statement. Intel has also emphasized the bandwidth over latency argument. What Dell and Intel see are ever increasing bandwidth demands on memory, not only from the CPU, but from the AGP and PCI buses as well. A cache miss while memory is responding to an AGP memory request can get very expensive. This makes any small difference in latency between RDRAM and SDRAM a lessor issue. The memory subsystem must have enough overhead and capabilities to fully service all of it's masters. Intel, unlike Wall Street which has a very short term outlook, must look at system design issues in the long term. To do this they had to take a very educated guess as to what software and applications will require of their processors and chipsets years down the road (Dell also did the same thing in their white paper). What Intel sees is that while PC133, DDR may provide a short term solution, these technologies do not provide them with a long term solution. They are very concerned about the ability to scale upwards. Neither PC133 nor DDR use high quality transmission line techniques. As speeds increase, the need to do so will also increase. Since Rambus has patented their techniques, finding an alternative method not subject to Rambus patent infringement, may prove to be difficult. Add to that Intel's desire to incorporate a memory controller onto the processor chip, Rambus with it's low pincount becomes very desirable. They see the need to start the transition somewhere, sometime. If not now, then when?Rambus 300/600 has the streaming data advantage and a bandwidth that is 50% higher than PC100 - yet 300/600 has been rejected as too slow to compete with PC100 (it's as fast as, but more expensive than PC100). If the problem isn't latency, what is the problem? That's a nice question, but a question that no one can really give a final answer to, particularly when RDRAM is just now ramping up this quarter. Until the IDF at the end of this month, when Intel will release Camino specifications and test results, the best anyone can do is speculate based on tests using beta chipsets. And I believe those having beta chipsets are also under non-disclosure agreements. This has certainly led to an environment where there is much fiction to go with the facts. I will wait till the end of the month before I try to draw any conclusions. But I can hardly see where the question you raise will have any bearing on the long term acceptance of Rambus or not. If those 300/600 RDRAM chips end up in games or graphic boards, great. Regards, Jim