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To: unclewest who wrote (26951)	8/11/1999 9:51:00 PM
From: Jdaasoc	Read Replies (1) \| Respond to of 93625

Unclewest From Aug 10 patent office search. Microsoft files for settop box with RDRAM in it. 164.195.100.11 United States Patent 5,936,677 Fries , et al. August 10, 1999 -------------------------------------------------------------------------------- Microbuffer used in synchronization of image data Abstract For use in a set-top box, a relatively small line buffer and a frequency control permit scaling of a video input signal and synchronization between the input signal and a composite output signal. Image data and timing signals derived from the video signal are applied to a video capture engine (VCE). When scaling the input video, the VCE combines an appropriate number of successive lines of the field being processed to produce scaled scan line data for use by a dynamic composition engine (DCE) in producing the composite image. A video odd timing signal is applied to an input odd register, which is monitored by a central processing unit (CPU). The CPU controls the values in a frequency register and in an output odd register. The value in the frequency register determines the frequency of an output clock. The signal from the output clock is applied to a horizontal timing logic circuit that produces an output horizontal sync signal. By adjusting the values in the frequency register and in the output odd register, the CPU is able to control synchronization of the composite image and to determine whether the scaled video is rapidly synchronized with the input signal or is allowed to synchronize more slowly, after a change occurs in the video source. Preference can thus be given either to the stability of the digital signal portion of the composite image or to the scaled video data. -------------------------------------------------------------------------------- Inventors: Fries; Robert M. (Redmond, WA); Keam; Nigel Stuart (Redmond, WA) Assignee: Microsoft Corporation (Redmond, WA) Appl. No.: 928277 Filed: September 12, 1997 .... PCI bus 72 is coupled to a PCI slot 74 and to an application specific integrated circuit (ASIC) dynamic composition engine (DCE) 76. DCE 76 is connected to 16 Mbytes of RAMBUS dynamic random access memory (DRAM) 78. The DRAM is used for storing image data representing objects to be displayed on the display screen of television receiver 40. Network and cable tuners 82 are connected to receive video signals from an antenna, cable, or other source of video signals. Digital data conveyed by the video signals are input to PCI slot 74 and the analog video data are input to an analog-to-digital converter (ADC) 81, which converts the analog signal to a corresponding digital signal for input to DCE 76. The audio portion of the signal input to network and cable tuners 82 are input to a video/audio interface 80, which drives the video display device, i.e., television receiver 40, with an appropriate television broadcast signal format (or if a video monitor is being used in lieu of a convention television receiver, the appropriate video drive signals required by the monitor).