SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Charles R who wrote (68804)8/14/1999 11:46:00 AM
From: Cirruslvr  Read Replies (1) | Respond to of 1573816
 
Chuck - RE: "I wonder how a CuMine which has half the L1 and half the L2, but at full speed, would fare."

Do you know for sure if Cuontimemine will have a 64KB L1 cache?

If so, I would like to see benchmarks of a K6-III w/o L3 cache and Cuontimemine at the same MHz, assuming AMD can get the K6-III any higher in MHz. I believe this will be the first time someone will be able to do a true comparison (w/o completely disabling any caches) of Intel's and AMD's sixth generation processors.

Cuontimemine will still blow away the K6-III in FPU, but business benchmarks would be interesting.



To: Charles R who wrote (68804)8/14/1999 12:01:00 PM
From: Dan3  Respond to of 1573816
 
Re: I was thinking AMD would use Dresden to get some high speed SRAMs

It would sure make sense. One part that has been shipping in copper, in volume, for a while is Motorola SRAM - and isn't it pretty much a modified Motorola process that's being used at Dresden?

mot.com

note the 50-75% power reduction and the 9/23/1998 date.

Dan