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To: visionthing who wrote (27255)	8/18/1999 11:12:00 PM
From: MileHigh	Respond to of 93625

IBM plans 500-MHz bus for Power4 processor By Will Wade EE Times (08/18/99, 6:14 p.m. EDT) PALO ALTO, Calif. — IBM Corp. expects its next-generation Power4 microprocessor to communicate with other chips in a system using a 500-MHz bus. Detailing the design at the annual Hot Chips technical conference this week, IBM said the bus' increased bandwidth will be essential to delivering higher performance in upcoming servers and workstations. "How the microprocessor communicates with the chip set is critical," said Frank Ferraiolo, a senior engineer on the design team of the Power4 processor. "With current technology the bandwidth is limited, so the processor is data-starved." Even as MPUs pass the 600-MHz barrier and continue to process more data internally, Ferraiolo noted, power is not used effectively because it can't be pushed off the processor at the same speeds. Bus speeds of 100 MHz, beginning to migrate to 133 MHz, dominate current designs. IBM uses a technology known as a synchronous wave-pipelined interface, or an elastic interface, for the Power4 I/O. The key is controlling latency. Not only does the design minimize latency as data moves on and off the chip, it also has a FIFO on the receive side so the processor can synchronize data transfers. Latency issue Conventional interface timing is dictated by latency, Ferraiolo said, because the bus clock period must exceed the worst-case latency of the interface to prevent possible data loss. Using an elastic interface, the latency period can be controlled and this problem is eliminated. "That allows the bandwidth of the interconnect to determine the speed of the bus," he said. This is especially important for multiprocessor designs, where several MPU cores on the same die must receive data in parallel to process the information at the same time. The Power4 chip has been engineered for multicore processing and will initially be implemented with two processor cores. Ferraiolo said elastic timing is critical to make sure that data traveling different distances across the chip to each core must arrive to be processed in the correct order. "This gives us great flexibility in modifying and enhancing microprocessor performance," he said. Though the Power4 is not yet in production, IBM has a test chip running in the lab. Produced with 0.18-micron technology, it features all-copper interconnects through its seven layers of metal and is built using silicon-on-insulator (SOI) wafers. With current versions of the Power4 topping 500 MHz, it is expected to deliver more than 1 GHz of performance eventually. A Power4 called the Pulsar, which is to be launched in IBM's RS/6000 servers, will be produced at the 0.18-micron level, with copper.