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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Alan Bell who wrote (27535)	8/24/1999 11:41:00 AM
From: Bilow	Respond to of 93625

Hi Alan Bell; Regarding the use of both edges of a clock to capture data. This is a common enough expedient in digital design. You can extract double clocked data from a line using a (somewhat looked down upon) technique that generates a pulse with each transition of the incoming clock. (Use a delay element and an XOR gate. Just don't say I told you to do this. The basic problem is that it takes more effort to analyze a design for worst case if it includes this sort of clocking scheme.) It is more complicated to use both edges, but it divides the clock frequency by two. Even at low clock frequencies this is useful in that it reduces radiated power (i.e. you can pass FCC easier). Another common technique for reducing clock frequencies is to use a local clock frequency multiplier. The new Xilinx chips (i.e. Virtex) include four programmable DLLs on chip. Using this technique, two Xilinx chips can pass data back and forth at twice the applied clock frequency. You can also gang them, and pass data at four times the applied clock frequency, though working out the worst case analysis is harder. Here's a link: (pdf) xilinx.com Note that the last time I looked, the above link has obsolete jitter specifications. The new numbers are in the Virtex data sheet and are much, much better (60ps worst case.) I doubt that using both edges is patentable. It surely comes under the classification of "prior art," probably mentioned in someone's thesis in the 40s or 50s. I spent 10 minutes looking for a patent number, but it is hard to do the search. The Rambus patents do not appear to mention that particular as being patented, but they are numerous and I certainly didn't look more than cursorily at them. That said, RMBS's particular implementation includes a lot more than just double clocking. I am more familiar with the DDR SDRAM interface, which also double clocks the data. In that scheme, there is a data clock that is bidirectional. There is also a clock for each chip that is free running. The data clock has to be turned on and off, and the details of how and when that is done are presumably patentable. -- Carl