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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: THE WATSONYOUTH who wrote (70330)	8/30/1999 7:02:00 PM
From: Elmer	Read Replies (2) \| Respond to of 1573714

Re: "This local interconnect level allows a 12% - 15% advantage in SRAM cell size and a somewhat smaller advantage in logic density. However, it comes at a price. It is a difficult level from a processing point of view and, if not done correctly, a source of significant yield loss. My understanding is that AMD eliminated this level in the K7 design, opting for the more conventional easier approach. If so, this is probably a smart move on their part and may enable them to yield large L2 caches much more easily. Can anyone familiar with the history of K62/K63 confirm the local interconnect as being the main yield detractor and whether or not AMD did, in fact, abandon it in the K7 design? I asked this question in an earlier post and got ZERO response." I have been making this exact point for a very long time. No one though has commented on the yield impact of the local interconnects. If it has been the main source of yield loss, AMD would do themselves a favor by dropping it but the die size increase would affect the fab capacity, especially with ondie L2. This is a perfect example of an architects dreams not matching up with manufacturing realities. I believe Intel has avoided LI for the reasons you state, opting instead for higher yields and faster throughput, at the cost of die area. PB, do you know if Intel has any plans for LI on a future process? EP

To: THE WATSONYOUTH who wrote (70330)	8/30/1999 7:48:00 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1573714

<Can anyone familiar with the history of K62/K63 confirm the local interconnect as being the main yield detractor and whether or not AMD did, in fact, abandon it in the K7 design?> K7 is 22 million transistors squeezed in 180 mm2. Pentium III is 9.5 million transistors in 140 mm2. Judging from this alone, my guess would be that AMD is still using local interconnect for K7, at least on the 0.25 micron process. I don't know whether LI was the main detractor of K6-x yields, though. Tenchusatsu