Process Boy and thread, Article... Intel, IBM face off in gambit that spurns ASICs for standard processors -- Chip giants ante up for comms
August 31, 1999
ELECTRONIC ENGINEERING TIMES : SANTA CLARA, CALIF. - IBM Corp. today will detail a slew of architectures and initiatives-including a network processor integrating 10 RISC cores-as its microelectronics division drives toward a broad offering of merchant communications silicon. Meanwhile, Intel Corp., leveraging two recent acquisitions in communications chips, this week will publicly sketch out plans for devices that will serve a broad spectrum of public and private data networks.
The two semiconductor giants will go head-to-head as they apply their process technology prowess to redefine themselves as building-block suppliers for the next generation of Internet equipment. Both hope to ride the coattails of a trend among systems makers to build fewer costly and time-consuming ASICs for each new product and rely more on standard programmable processors.
Responding to the trend, IBM, itself a major ASIC producer, "is looking at migrating the industry from an ASIC model to a network processing model" via new silicon and programming tools, said Steve Longoria, the microelectronics division's marketing manager for wired communications.
And as Intel moves beyond a PC-centric focus, its "mission is changing and broadening," said Mark Christensen, vice president of Intel's Network Communications Group. "The entire infrastructure of the Internet will upgrade over time, and we want that to be with Intel technology."
At its developer forum in Palm Springs, Calif., this week, Intel will reveal some of its plans for a full suite of communications coprocessors. The chips, detailed privately in analyst meetings last week, include Layer 3 header processors that use technologies from new Intel subsidiary Level One Communications Inc. (Sacramento, Calif.) as well as a midrange processor that runs at 266 MHz and uses several RISC processors in parallel. The net chip will use the StrongARM, plucked from Digital Equipment Corp., as an executive controller for administrative tasks and scheduling among a series of smaller engines that will handle packet parsing and serial line aggregation.
At the high end of Intel's offerings will be 64- and 128-bit wire-speed packet-forwarding engines from Softcom Microsystems Inc. (Fremont, Calif.), which Intel acquired in July. And Intel is expected to repeat a statement that drew gasps from some of the analysts briefed last week, announcing that it will tap its x86 and Pentium cores as primary processors in switches and routers. The x86 CPUs would be central controllers; the Level One, StrongARM and Softcom engines would be coprocessors.
Missing from Intel's end-to-end strategy, at least for now, is a switch fabric.
Analysts had mixed reactions to the Intel briefing last week. Some saw a grand strategy spanning business, edge and carrier networks. Others said the company still lacks a credible, coherent vision.
"Don't forget that Intel is the same company that abandoned the i960 because it needed the fab space to make more desktop microprocessors. They need to overcome some understandable skepticism among potential customers," said principal analyst Frank Dzubeck at Communications Network Architects Inc. (Washington). "Right now, they have nothing other than some separate elements. They are not paying attention to the materials-science side of things. IBM says, 'We have a rich suite of copper, silicon-on-insulator, and silicon germanium we can apply to this problem.' Intel does not have any of that."
For its part, IBM this week will unveil a home-grown network processor for 4-Gbit networks and a lower-end processor for networked resources for midrange edge switching. Also on tap is a 28.4-Gbit/second packet-routing switch, the latest generation of the Prisma physical-layer switching fabric family, that could link to network processors from multiple vendors.
While not following Intel down the acquisition trail, IBM has picked up two partners. Net processor startup C-Port Corp. (North Andover, Mass.) will work with Big Blue to work on open application programming interfaces that would ease application development. And IBM will act as a foundry for PMC-Sierra Inc. (Burnaby, B.C.), which will tap Big Blue's quarter-micron CMOS to make the 2.5- and 10-Gbit/s network switching chip set that PMC acquired last week as part of its $400 million purchase of Abrizio (Mountain View, Calif.), a startup formed by veterans of Stanford University's Tiny-Tera project.
The Abrizio switch, developed at Stanford University with investments from Texas Instruments Inc. and Cisco Systems Inc., is a four-chip set capable of supporting OC-48 and OC-192 ports. Two of the four chips have been taken through initial silicon prototypes, and Abrizio already is at work on a second generation.
IBM appears to be carving an open path. Along with C-Port, it is a member of the Common Switch Interface (CSIX) consortium, which is defining a published interface between Layer 1 switching fabrics and Layer 2 and 3 bridging and routing processors. The practical benefit of CSIX for IBM, according to Longoria, is that C-Port's C-5 processor (see Aug. 16, page 1) could be linked directly to IBM's 28.4-Gbit/s packet-routing switch. IBM's network processors, conversely, could be linked to alternative switching fabrics from CSIX-compliant vendors, such as the Tera Channel fabrics from Power X Ltd. (Manchester, England).
In addition, IBM is opening communications R&D centers in Yorktown Heights, N.Y; Zurich; and Haifa, Israel, to work with customers on advanced switching systems and on new protocols for routing and switching.
Topping IBM's announcements is the high-end network processor, code-named Rainier. It is based on 10 PicoProcessor RISC cores, operating in parallel on packet parsing and other tasks. Built from scratch at IBM, the PicoProcessor is a RISC engine that has been optimized for data networking.
The 10 processors, with an aggregate processing power of 1,333 Mips, are fed by a centralized embedded PowerPC.
PicoProcessors are programmable, meaning Rainier's ports can be software-configured for asynchronous transfer mode or Ethernet, for example. Functions such as ATM segmentation and reassembly are programmable on Rainier but are fixed on the midrange chip.
The processor features dedicated Ethernet medium access controllers-40 10/100 ports or four Gigabit Ethernet ports-but its flexibility is key.
The processor for network resources is a mixture of programmable and hardwired blocks, including a PowerPC 133-MHz 401 core. The part is aimed at OC-12 (622-Mbit/s) speeds. It includes dedicated blocks for ATM segmentation and reassembly, Sonet framing and PCI interfaces.
While IBM's network processors are built on standard CMOS, the high-end Rainier will shift to copper interconnects soon, Longoria said. IBM sees CMOS " running out of gas" beyond OC-48 (2.5-Gbit/s) speeds, which could open the door to processors built of silicon germanium, he said.
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