Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Glenda King who wrote (28573)	9/2/1999 7:36:00 PM
From: dumbmoney	Read Replies (2) \| Respond to of 93625

Good EETimes article, new info: eetimes.com The newly-announced Rambus Implementers Forum includes Hyundai, Micron, NEC, Samsung, Infineon and Toshiba, as well as Intel and Rambus. One of its biggest chores will be to tame the memory-bank problem. MacWilliams said the forum may come up with one or more commonly accepted RDRAM designs with fewer memory banks, which would then be supported by iterations of the Intel chip sets. One suggestion is to trim the number of memory banks per chip to a single set of 16 dependent banks; another calls for four independent banks. The final decision "is up to each vendor, and over time Intel would build chip sets that would support different approaches," he said. Three years ago, Rambus engineers thought adding banks would allow the Rambus technology to offer on-chip concurrency, fetching bits from multiple banks at the same time. The goal was to reduce first-access latency, an issue that dogged RDRAM's performance in the early going. Geoff Tate, chief executive officer of Rambus, said that over the past few years, Rambus and the RDRAM vendors have come to realize that having so many on-chip memory banks made it more difficult to efficiently lay out the redundancy bits needed to keep yields at respectable levels. Adding redundancy bits for each bank added to the chip's die size, and thus increased costs. Cutting redundancy bits can also raise costs by reducing yields. "If we knew then what we know now about the die size impact, we would have decided on fewer banks. But the issue is not just reducing the number of banks, it is making sure there is compatibility among the various DRAM vendors," Tate said. Tate said he expects the memory-bank issue to be decided in the next few months. As vendors create new mask sets for shrink versions of the various 128-Mbit RDRAM implementations, the reduced-bank design would be implemented.