Notes on SSTL_2, DDR, and why DDR data busses may be used as bidirectional transmission lines, also on why the motherboard makers hate rambus.
Micron website for DDR:
micron.com
From the 128MB data sheet:
(page 1) 2.5V SSTL_2 compatible I/O.
This means that the inputs and output voltage levels &c. are defined to the SSTL_2 standard.
(pdf) micron.com
Just looking at the SSTL levels is probably enough to convince any EE that the logic is suitable for transmission line driving. They even include voltage level standards that assume a little underdamping at the termination. But finding a link that would show this to the uneducated took some time. But I did find a lot of other interesting stuff, and will post it later. Anyway, the SSTL_2 standard is defined in EIA/JEDEC specifications. Here are the definitions of a bunch of low voltage interface standards, for future reference:
jedec.org
SSTL_2 stands for "Stub Series Terminated Logic, 2.5 volt.
If you'll take a look at page 19 (of 21-page pdf file, but labelled as page 13) of the following document, you will see a 50 ohm transmission line. Data is shown being passed from the left to the right. The text reads: Finally, the system designer may require a bus system which must be terminated at both sides. This is the description of a bidirectional bus. The drawing shows data only going one way, as such a bus only passes information in one direction at a time:
jedec.org
This should pretty much demonstrate to the casual engineer out there that SSTL_2 is designed for driving transmission lines.
The uneducated would, no doubt, not recognize a bidirectional transmission line logic family if it came up and had unwanted, unprotected sex with them. For this reason, I now visit the Rambus web site to get quotes from the rambus logic definitions...
rambus.com
The first thing you notice about the above site is that it is strongly biased in favor of the investor rather than the engineer. DOESN'T THAT MAKE ANY OF YOU A LITTLE WORRIED? Engineers have to click off to the Developer Site. But Company Relations, News, and Investor Relations is given a front row seat. Ah, here it is, the 128/144MB RDRAM specification, only 1MB, so you guys should down load a copy:
rambus.com
Unfortunately, I couldn't download the above, (maybe my link is too slow), but here is the "short channel design guide," which applies to PCB designers who use the simpler version of direct rambus channel (i.e. bus connections). This is great reading for those of you who still think that rambus technology is no bid deal for the motherboard house. Here are some great things to have to inform your PCB layout artist:
all RSI, data signals the SCK and CMD CMOS signals, and the differential clock pairs must have matched electrical lengths between the controller and any RDRAM on the Channel Hmmm...
Rambus recommends against critical signals making right-angle turns, but having many 45 degree turns will be unavoidable. The length of each 45 degree turn should be a minimum of 2mm to avoid a local impedance depression. I can't help it, I'm laughing so hard I can barely type!
The loading effects of the RDRAM package and I/O circuit would tend to lower the impedance of the Channel at the points where the RDRAMs are connected. To offset this effect, the width of the trace near the RDRAM load is reduced. (Snicker, snicker. So much for the guy who complained about mixing memory makers. With any particular rambus channel, you are going to have to have all the slots occupied. No big deal to the user, but it means that if you want to sell two different memory sized DIMMs by having some positions unfilled, you are out of luck. Instead, you will have to design another PCB for the lightly filled DIMM. This adds costs to the DIMM maker, as he has to design and stock more kinds of PCBs.)
In many places, vias will drill through the ground and power planes, resulting in holes the planes. If these holes are close to each other and of sufficient size, they will overlap and effectively crate a slot in the plane. This is of particular concern near the small-pitch RDRAM footprints. Planes to which RSL signals are referenced must have no slots that impede the return current. Oh boy!
matched propagation delays from the controller die pads to the first RDRAM in order to minimize the skew between these signals at the input pins of the devices on the Channel. Matching the trace lengths on the motherboard is not sufficient to minimize the skew between signals. The motherboard designer must also account for other factors that cause skew between the signals... The controller package, the controller pin escape routing, and vias. Additionally, since the propagation delay of a signal depends on its mode of propagation (odd or even), clocks that are routed differentially will propagate faster than the data signals. I'm sure a lot of this seems quite simple to you guys, but this is not going to be a painless experience for the box makers. As for making these Channels longer than around 8 inches, in your dreams. It really stuns me that people are considering going through these kinds of hoops just for the disadvantage of paying an extra 35% for their memory. Anyway, on page 9 of 29, marked as page 4, you will find the drawing that shows the transmission lines for the rambus clocks. Just like the transmissions lines in the above SSTL_2 article. Link to (hilarious) rambus PCB design guide:
rambus.com
One of the worst problems in managing problems in complicated digital design is apportioning blame when things don't work. This is not so much for financial considerations, but for determining who made a mistake, and, therefore, who needs to alter their work. The effect of these incredibly complicated PCB instructions is that when a box maker has a design that is failing to work on 5% of the manufactured computers, they will have a very hard time proving whether it was the memory maker (i.e. Micron), the controller maker(i.e. Intel), or the board maker (i.e. themselves) who failed.
-- Carl |
