SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Ali Chen who wrote (71644)9/10/1999 6:12:00 PM
From: Yousef  Read Replies (2) | Respond to of 1573980
 
Ali,

Re: "The SRAM address decoders and D-triggers are much simpler than
CPU logic structures, therefore your implication is not valid."

What you say may be "correct", but your conclusions are wrong again ... and
again. <ggg> Please review the slide that shows the layout of the chip.
Even you will notice the large distance needed to be "driven" by
small FET's in the core. The issues are different as you point
out, but FET drive current is still the key issue (at .18um) that
will increase both the SRAM and CPU speed. This is indeed the correct
conclusion my "amateur CPU designer". <ggg>

Make It So,
Yousef