To: Douglas Raushel who wrote (3822 ) 9/20/1999 11:22:00 AM From: Tom Shutters Respond to of 4005
"Enhanced Tools Help Uphold The PLD's Reputation -- Design-verification tools are critical for maintaining programmable logic's key advantages-time-to-market and flexibility." ..."One crucial factor often overlooked in the design-verification stage is what's happening inside the chip"... ..."Actel Corp. has added a similar logic-analysis capability to its antifuse and upcoming SRAM architectures. "Action Probes" embedded in the form of cores allow the in-circuit routing of any of the internal nodes out to a couple of points to test things at speed without changing any of the functionality of the chip"... ..."An Actel customer working on a data-acquisition instrumentation design was able to quickly find and fix a design problem by using the probe capability provided in the company's development tools, Colleran said." "The design worked at room temperature, but after running for a few hours in the lab, it no longer functioned correctly. Using the probe technique, the customer found that he had built in a "race condition" (in which a glitch in the circuit can result if one signal gets to a certain point before another) and was able to quickly correct the problem and get the product to market"... ..."a lot of leading-edge verification work is being done for ASICs, which will eventually find its way into the PLD community"... ..."Actel has been working with Synopsys to adapt the Formality formal verification tool to its new flash-based ProASIC architecture. The ProASIC devices, developed by Gatefield Corp., Fremont, Calif., and marketed by Actel, recently began shipping in sample quantities"...techweb.com