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To: kash johal who wrote (29273)	9/11/1999 5:28:00 PM
From: Bilow	Respond to of 93625

Hi kash johal; Your analysis of John's post Re: power consumption is correct. It would ruin random access times to leave parts in nap mode, rather than STBY. And he also incorrectly assumed that SSTL_2 is a logic family that requires DC currents to maintain signals. The correct calculation would use the capacitance, frequency, and the voltage swing of the wires, and since the SDRAM only load each data line with two chips (i.e. the controller and the DRAM), the capacitance should be quite small. He is also still misestimating RDRAM output power calculations in the read mode, by assuming that he can use VOL and IOL for the CMOS outputs to compute the power consumption of the 400MHz outputs. This is the note (b) that applies to RDRAM read states. Because of this, he has his RDRAM read power spec much lower than the write power consumption. As far as his statement that Samsung is coming out with bigger RDRAM chips soon, it is also true that Samsung is already offering bigger SDRAM chips, and, in addition, they are claiming a new design that allows them to produce DDR an SDRAM from the same die. This means that their DDR chips will track their SDRAM chips immediately in size and performance in the future. -- Carl

To: kash johal who wrote (29273)	9/12/1999 5:03:00 AM
From: John Walliker	Read Replies (1) \| Respond to of 93625

Kash, I believe that there are 2 mistakes in your calcs: 1. Devices will not be in NAP mode. 2. And you grossly misinterpret the power consumption of the I/O portion of DDR-DRAM I also calculated the supply current assuming no use of NAP mode - look again at my posting. Please show me how I should have calculated the power consumption. I assumed that logic 1s and 0s would have equal probability. That the RSL logic 1 current is about 30mA (based on the signalling level and bus impedance). That logic 0 current is zero. What is wrong with this? John