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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: grok who wrote (29298)	9/12/1999 3:53:00 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi KZNerd; Regarding computers sending reads and writes all around the memory, I agree completely. I didn't mean to imply that designers were going to leave RDRAM in NAP mode, but only that all but one chip in a channel would be in STBY mode. I agree that assuming that all but a couple chips would be in NAP mode is unlikely. It would occur for long periods of time, only if the guy who bought the computer had way too much memory installed. This is possible, of course, but engineers need to design for worst case. There are several things I still want to talk about on this board: (1) Actual and worst case power consumption figures for a rambus channel. The figures have been done so badly that it is funny. But these are complicated and time consuming, so this may take some time. In addition to the silly use of CMOS VOL and IOL errors in previous analyses, there is also a post on this thread suggesting that the channels only consume power when changing state. I believe that this is contrary to rambus's RLS logic definition being a "wired-or" logic type. (In other words, no tristate is needed.) But I would have to go study a lot more stuff to make sure of my calculations, and it is going to depend on the trace impedance chosen by the motherboard maker, which is, of course, subject to technical limitations. (2) Actual rambus memory latency. There is a fascinating interaction between granularity and latency that would be most interesting to discuss: As the rambus granularity decreases, the effective latency increases. (On the other hand, as the granularity increases, the power consumption also increases. Because of this, we have a classic engineering problem of balancing two conflicting design goals.) I would like to work out a complete example with timing diagrams, for a memory system connected to the Athlon, for PC100, PC133, DDR, and RDRAM. (3) I would like to estimate the added parts and labor cost to the motherboard maker to support RDRAM. In addition to the more expensive memory, there are also costs associated with the power supply for the rambus channel termination voltage. (When choosing the termination voltage power supply, a trade off between cost and power consumption is required. The power consumption calculations in the rambus data book compute the supply currents to the RDRAM chips themselves, and, when in read mode, the power consumption associated with driving a logic one. This ignores the power consumption in the termination resistors and the termination power supply.) I do have some wretched imitation of a life, and don't have an infinite amount of time to devote to this thread, so if you would like to address the above, please feel free. -- Carl