SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Rob Young who wrote (88161)9/12/1999 4:27:00 AM
From: Tenchusatsu  Read Replies (1) | Respond to of 186894
 
<Running PA binaries in emulation mode result in about 90% native integer PA 8500 performance. Since PA 8500 does 34-35 or so integer, Merced does about 31-32 int running emulated PA-RISC binaries (translated on the fly).>

These PA-RISC binaries were run on simulators, meaning that clock speeds were assumed to be equal. Right now, PA-RISC runs at a pretty low clock speed of 440 MHz. Care to guess whether Merced will have a faster clock at its release than PA-RISC?

<Looking at the base IA64 instruction set, I'd say that the IA64 is extremely similar to PA-RISC -- most of the instructions look like they were just copied over, then this bundle/predication/windows/multiway branch stuff heaped over it.>

And I suppose all that bundle/predication/windows/multiway branch stuff does absolutely nothing for IA-64 performance.

Or perhaps all of these features combined is the key to IA-64's advantage over PA-RISC? Nah, it's obvious that all of those claims of high performance by the Merced people can easily be dismissed with a single "I doubt it" statement from an anonymous CPU architect.

Tenchusatsu