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To: John Walliker who wrote (29485)	9/15/1999 6:24:00 PM
From: Bilow	Respond to of 93625

Hi John Walliker; Re: PS Yes, I did forget to compensate for the 10ns cycle time rather than 8ns as Carl pointed out. However, he was wrong to assume that power consumption scales linearly with frequency, because the sense amplifiers will draw a relatively constant current. This is a difficult thing to check. I believe that the DRAM sense amplifiers are part of a self-timed circuit, and therefore use a certain amount of energy per access. That is, they do not leave the sense amps active all the time. Self-timing is inherent to all the non-synchronous families of DRAM. I was under the impression that this self-timing was still used in the cores of SDRAM, and, presumably, DDR SDRAM, and that these more modern families only use the input clock to synchronize the inputs and outputs. (This is from a conversation I had with a Fujitsu memory rep about 8 years ago.) As an example of the self-timed nature of internal DRAM operation, you can look on pages 388/370 and 390/372 of the following IBM data book, (for their standard cell embedded DRAM): (big pdf) chips.ibm.com In the above timing diagram, note that a single falling transition of MSN is sufficient to access the first word of data, and that no other input changes are required. Instead, the first word of data just comes out (after a time delay of tACC). Subsequent data is accessed by falling transistions on the PGN line. After that first falling edge of MSN, the DRAM has to do a sequence of things. First the memory row is read, then that data is written back into the array. Since we know that they have to self-time this sequence of events, wouldn't it be logical to suppose that they also self-time the power to the sense amps? I know it would be easier for them to just let them burn up power, but engineers have a way of taking advantage of these sorts of things. Byn the way, power requirements for the DRAM are listed on page 386/368, and give active current for random access of 60mA, and active current for page mode of 5.5mA, so they are clearly reducing power in page mode. The only real way to figure this out is to call up the IBM reps, but that seems too much like work to me. I hate using the phone... Much prefer to surf. -- Carl