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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: dumbmoney who wrote (29699)	9/16/1999 3:32:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 93625

dumbmoney, <Briefly, there are 16 row caches (actually 1/4 row). A row cache can be filled by any row in any physical bank. Core operations (e.g. precharge) occur concurrently with row cache read/write.> Row caches. Fully associative. Ahhhh! Now I get it. I also see why this can't be duplicated in the memory controller. Seems like virtual channels allow you to gain the benefits of keeping pages open without actually having to keep the pages open (and risk the latency penalty due to precharging). This would benefit low-to-mid-range desktop systems. (But it won't benefit servers because they have no need to keep pages open in the first place.) <Incidentally, the VC concept is equally applicable to Rambus. It would solve the too-many-physical-banks problem they seem to be having.> I don't think it's as easy to do with Rambus. With SDRAM, a chunk of data usually comes from eight chips simultaneously (or four, or maybe even two), meaning that the row caches can be spread across the eight chips and address any row in any bank. With RDRAM, a chunk of data always comes from one chip at a time, meaning that the row caches must be contained in each chip and can only address rows and banks in that chip alone. In fact, I don't think Virtual Channel technology is very applicable to RDRAM. VCs are nice for memory systems with a small number of banks, such as SDRAM. But VCs are useless for memory systems with a large number of banks, such as RDRAM. And even if RDRAM reduced the number of banks, it's hard to implement VCs for the reasons mentioned in the previous paragraph. It will be interesting to see how Virtual Channels improve upon the inefficiencies of SDRAM, especially DDR SDRAM. Tenchusatsu