SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (29724)9/16/1999 10:28:00 PM
From: dumbmoney  Respond to of 93625
 
Sure, the row caches can help even if they are confined within a chip, but they won't be fully associative across multiple chips, which is a shame because there could be up to 32 chips on one RDRAM channel.

All that means is that the Rambus rows are narrower (but the VC SDRAMs only cache 1/4 row). Otherwise, it's a blessing, since the Rambus system will have more rows in cache, and hence a higher hit rate.


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News