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To: Elmer who wrote (88428)9/17/1999 1:38:00 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
Elmer - Re: "CuMines/Cascades with L2 cache sizes of 128K,256K,512K,1M&2M!"

The delivery schedule for the large cache Cascades is quite conservative.

I assume that is due to the large die size associated with these large caches.

By my count, the 2 Meg L2 cache adds a whopping 113,246,208 transistors - including redundancy ! The rest of the chip is probably only another 9 million transistors.

That chip ain't small !

Paul