Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : AMD/INTC/RMBS et ALL -- Ignore unavailable to you. Want to Upgrade?

To: unclewest who wrote (83)	9/18/1999 9:02:00 PM
From: Dan3	Respond to of 271

Re: if rmbs has an extra 10ns delay getting started... Most accesses are satisfied by the cache, particularly next address accesses - that's why memory requests deliver 32 or 64 bytes instead of just one to the cache, that's where the big caches in modern CPUs shine. But the 10ns gets made up, and Rambus can actually pull ahead, in the next call to main memory if such does occur after subsequent accesses exhaust the cache line and the controller has been smart enough to fill a cache line with the contents of the next set of memory addresses. Which sort of begs the question - now that you've brought it up - how DOES the system know to fill more than 1 cache line? You can't just do it all the time, you'd wipe out the whole cache with every call to memory. Maybe that's why the performance results are coming back so underwhelmingly. Can someone step in here regarding when do you ever use rambus's streaming memory capability other than in a video frame buffer class of operation? 10ns doesn't sound like very long, but modern processors are superscalar, that is, they execute more than 1 instruction per clock. So, if each clock is worth 1.5 instructions, and we consider a Pentium III, or Athlon running at 667MHZ, we lose 10 instructions during that 10ns delay. unclewest, please feel free to respond Dan

To: unclewest who wrote (83)	9/19/1999 2:01:00 AM
From: kash johal	Respond to of 271

Uncle, Re: "rambus performance" I guess it is becoming clearer to me that current Rambus chips will be competing with ONE arm tied behind their backs. Apparently power consumtion is so high that chips will not be in an active mode all the time. Now power consumption goes down as we move from 0.25 to 0.18 and then to 0.15. Does that mean that in a few years is when Rambus memories can operate at their full potential when power ia cut by 50% by moving down the technology curve. It seems to me that OEMs refused to go along with the Rambus wind tunnels that could have cooled the chips effectively. Is my understanding correct on this or am i in left field here. regards, Kash.