Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (88610)	9/21/1999 11:47:00 PM
From: Paul Engel	Respond to of 186894

Dannie 69-66 - Re: "How many additional cycles are required to fetch from level 2 on Coppermine when there is a cache miss in level 1? Is it just 1 extra clock? " Several FEWER CYCLES are required for an L1 cache miss on the Coppermine than on the Athlon - which has to go OFF chip to a SLOWER L2 cache. By the way, did you know that that 128K L2 cache on the Athlon is responsible in large part for the huge die size - 184 sq. mm. - 73% LARGER than the Coppermine? Now you know why they are "hard to find" - because they are "hard to yield" ! Paul

To: Dan3 who wrote (88610)	9/21/1999 11:52:00 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

Re: "It's too bad that Intel couldn't get the level 1 cache on Coppermine past 32K. I'll bet performance would be increased if it had the 128K level 1 cache Athlon has. How many additional cycles are required to fetch from level 2 on Coppermine when there is a cache miss in level 1? Is it just 1 extra clock? " One website is reporting the Coppermine will have 64K L1 to compliment the 256K(and greater) L2. I don't know if this is true or not but the same rumors were spread about PIII before it's release. I am not a processor architect so I am only guessing but I would think it would be only 1 clock as the memory requests would be dispatched to both L1 & L2 simultaneously. Someone else will hopefully comment. EP

To: Dan3 who wrote (88610)	9/22/1999 1:42:00 AM
From: Tenchusatsu	Read Replies (3) \| Respond to of 186894

Dan, <How many additional cycles are required to fetch from level 2 on Coppermine when there is a cache miss in level 1? Is it just 1 extra clock?> Nope. The latency of the on-die L2 cache is eight clock cycles. This is true for Coppermine; I think it's also true for Mendocino (Celeron) and Dixon (Mobile Pentium II). This is better than the off-chip L2 cache of Pentium III, which I think was at least 18 clocks. Xeon's L2 latency is somewhere between 8 and 18. I don't know what Athlon's L2 latency is, but I'll bet it's comparable to Pentium III. Tenchusatsu