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To: Tenchusatsu who wrote (88673)	9/22/1999 8:53:00 PM
From: Paul Engel	Read Replies (2) \| Respond to of 186894

Ten - re: "Obviously, I would never be able to say that Mendocino Celeron can outperform an Alpha 21364 and keep a straight face. (Steve Jobs could if he worked for Intel, but that's a different story.)" If Steve Jobs worked for Compaq, he'd be SELLING 21364-based PCs & Servers TODAY ! The fact that it isn't "available" wouldn't even phase him ! Paul

To: Tenchusatsu who wrote (88673)	9/22/1999 11:23:00 PM
From: Rob Young	Respond to of 186894

Tench, Sorry.. we have had quite civil exchanges of late. But as you go back and read my "rant" you see it may be a bit warm in places but of all people I guess I can hold your feet to the "technical fire." Linley is grasping .. he is always grasping. I'm assuming Linley. Linley who has made the statement: "They [Digital] may decide to go ahead with 21364" as if it was on hold. The slides claim "improve single system performance:" digital.com So yes.. I can think of code (tpmC) that is very branchy and is the reason that Alpha has been somewhat an underperformer versus Intel and MSQL. However, Intel and SQL server are an outstanding transaction platform and the industry in general can't come down to the price performance they offer. MPR describes: <Its impressive 80-entry reorder buffer notwithstanding, the 21364 is unlikely to queue enough instructions to avoid stalling during a 12-cycle L1 cache miss.> 80 instructions in-flight is how they describe it. What about the 32 loads and 32 stores? Do celerons ever stall or Xeons, or is the attempt to point out that the 21364 will probably stall more oftn? It is probably again a matter of positioning and maybe cleanup. The 21164 cycle miss count improved when cleanup occured and the 21164A rolled out. What I suspect is that maybe for a 4 processor server target a 21264 at .18 micron and copper SOI process with L2 at 8 MByte DDR-SSRAM cycling 1 GHz may be an ideal 4 processor box. As you get into the 16 and 32 processor range (Wildfire .. Wildfire makes it worldwide preview October 11th in Europe by the way) the 21364 will be the top-dog. What MPR folks are overlooking and the slides highlight is: digital.com Network Interface: Direct processor to processor Routable 10 GByte/sec per processor So with a 16 processor machine the effective L2 (thank you directory coherence) is 16 * 1.5 MByte or 24 MByte ... it is getting too late at night to figure the aggregate delay .. I've done that before but local L2 is 12 nsec (been there , done that) worse case? With 16 processors, what 3 hops and only a few of them? 6 MByte of the L2 (one hop) is 15 nsec away as the slides show. Do you see one other thing? No need for L3. That makes for a very nicely priced server. Especially in the 8-16 processor range. Anyhow.. a 24 MByte L2 even if the outer reaches is < 30 cycles away. Tell me how many instruction misses you get in a heavy TPC environment with a 24 MByte L2 :-) Here is a block diagram: digital.com ----- Maybe the MPR folks are right about the stalls .. will have to dig around a bit. But remember also from Hot-Chips this year , Compaq improved 21264 hardware profiling and maybe it is doing much sweeter to even mask a 12 cycle penalty. Rob